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HD66727
(Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver with Key Scan Function)
Description
The HD66727, dot-matrix liquid crystal display controller and driver LSI incorporating a key scan function, displays alphanumerics, katakana, hiragana, and symbols. It can be configured to drive a dotmatrix liquid crystal display and control key scan functions under the control of an I2C bus or a clocksynchronized serial microprocessor. A single HD66727 is capable of displaying up to four 12-character lines, 40 segments, and 12 annunciators, and controlling up to a 4-by-8 key matrix, and driving three LED. The HD66727 incorporates all the functions required for driving a dot-matrix liquid crystal display such as display RAM, character generator, and liquid crystal drivers, and it also incorporates a booster for the LCD power supply and key scan functions. The HD66727 provides various functions to reduce the power consumption of an LCD system such as lowvoltage operation of 2.4V or less, a booster for generating a maximum of triple LCD drive voltage from the supplied voltage, and voltage-followers for decreasing the direct current flow in the LCD drive bleederresistors. Combining these hardware functions with software functions such as standby and sleep modes allows a fine power control. The HD66727, with the above functions, is suitable for any portable batterydriven product requiring long-term driving capabilities and small size.
Features
* * * * Control and drive of a dot-matrix LCD with built-in key scan functions Four 12-character lines, 40 segments, and 12 annunciators Control of up to a 4 x 8-key matrix, 3 LED ports and 3 general ports Low-power operation support: 2.4 to 5.5V (low voltage) Double or triple booster for liquid crystal drive voltage Contrast adjuster and voltage followers for decreasing the direct current flow in the LCD drive bleeder-resistors Standby mode and sleep mode Displays up to 12 static annunciators * I2C bus or clock-synchronized serial interface * 60 x 8-bit display data RAM (60 characters max)
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HD66727
* 11,520-bit character generator ROM 240 characters (6 x 8 dots) * 32 x 6-bit character generator RAM 4 characters (6 x 8 dots) * 8 x 6-bit segment RAM 40 segment-icons and marks max * 60-segment x 34-common liquid crystal display driver * Programmable display sizes and duty ratios (see Table 1) * Vertical smooth scroll * Vertical double-height display of all character fonts * Horizontal double display with dedicated character fonts (6-dot font width used) * Wide range of instruction functions: Clear display, display on/off control, icon and mark control, character blink, white-black inverting blinking cursor, icon and mark blink, return home, cursor on/off, white-black inverting raster-row * Internal oscillation with an external resistor * Hardware reset * Wide range of LCD drive voltages 3.0V to 13.0V * Slim chip with bumps for chip-on-glass (COG) mounting, slim chip without bumps for chip-on-board (COB) mounting, and tape carrier package (TCP) (under development) Table 1 Programmable Display Sizes and Duty Ratios
MultiplexedDrive Segments 40 40 40 40 StaticDrive AnnuScanned nciators Keys 12 12 12 12 32 (4 x 8) 32 (4 x 8) 32 (4 x 8) 32 (4 x 8)
Display Size 1 line x 12 characters
Duty Ratio 1/10
Oscillation Frequency 40 kHz 80 kHz 120 kHz 160 kHz
Current Consumption 8 A 15 A 23 A 30 A
LED Drive 3 3 3 3
General Port 3 3 3 3
2 lines x 12 1/18 characters 3 lines x 12 1/26 characters 4 lines x 12 1/34 characters
Note: Current consumption excludes that for LCD power supply source; V CC = 3V.
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HD66727
Type Name
Type Name HD66727A03TA0L HCD66727A03 HCD66727A03BP HD66727A04TA0L HCD66727A04 HCD66727A04BP External Dimension TCP Bare chip Au-bumped chip TCP Bare chip Au-bumped chip 2.4V to 5.5V PHS & Pager fonts Operation Voltage 2.4V to 5.5V Internal Font Japanese and European fonts
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HD66727
LCD-II Family Comparison
Item Power supply voltage LCD-II (HD44780U) 2.7V to 5.5V HD66702R 5V 10% (standard) 2.7 V to 5.5V (low voltage) 3.0V to 8.3V 20 characters x 2 lines HD66710 2.7V to 5.5V HD66712U 2.7V to 5.5V
Liquid crystal drive voltage Maximum display characters per chip
3.0 to 11.0V 8 characters x 2 lines
3.0 to 13.0V 16 characters x 2 lines/ 8 characters x 4 lines 40 1/17 and 1/33 9,600 bits (240 5-x-8 dot characters)
2.7 to 11.0V 24 characters x 2 lines/ 12 characters x 4 lines 60 (extended to 80) 1/17 and 1/33 9,600 bits (240 5-x-8 dot characters)
Segment display Display duty ratio CGROM
CGRAM DDRAM SEGRAM Segment signals Common signals Liquid crystal drive waveform Clock source Rf oscillation frequency Liquid crystal voltage booster circuit Liquid crystal drive operational amplifier Bleeder-resistor for liquid crystal drive Liquid crystal contrast adjuster Key scan circuit Extension driver control signal Reset function Horizontal smooth scroll Vertical smooth scroll Number of displayed lines Low power control Bus interface Package
None 1/8, 1/11, and 1/16 9,920 bits (208 5-x-8 dot characters and 32 5-x-10 dot characters) 64 bytes 80 bytes None 40 16 A External resistor or external clock 270 kHz 30% None None External None None Independent control signal Internal reset circuit Impossible Impossible 1 or 2 None 4 or 8 bits 80-pin QFP1420 80-pin TQFP1414 80-pin bare chip
None 1/8, 1/11, and 1/16 7,200 bits (160 5-x-7 dot characters and 32 5-x-10 dot characters) 64 bytes 80 bytes None 100 16 B External resistor or external clock 320 kHz 30% None None External None None Independent control signal Internal reset circuit Impossible Impossible 1 or 2 None 4 or 8 bits 144-pin FQFP2020 144-pin bare chip
64 bytes 80 bytes 8 bytes 40 33 B External resistor or external clock 270 kHz 30% Double or triple booster circuit None External None None Used in common with a driver output pin Internal reset circuit Dot unit Impossible 1, 2, or 4 Low power mode 4 or 8 bits 100-pin QFP1420 100-pin TQFP1414 100-pin bare chip
64 bytes 80 bytes 16 bytes 60 34 B External resistor or external clock 270 kHz 30% Double or triple booster circuit None External None None Independent control signal Internal reset circuit or reset input Dot unit and line unit Impossible 1, 2, or 4 Low power mode Serial, 4, or 8 bits 128-pin TCP 128-pin bare chip
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HD66727
LCD-II Family Comparison (cont)
Item Power supply voltage Liquid crystal drive voltage Maximum display characters per chip HD66720 2.7V to 5.5V 3.0 to 11.0V 10 characters x 1 line/ 8 characters x 2 lines 42 (extended to 80) 1/9 and 1/17 9,600 bits (240 5-x-8 dot characters) 64 bytes 40 bytes 16 bytes 42 17 B External resistor or external clock 160 kHz 30% HD66717 2.4V to 5.5V 3.0 to 13.0V 12 characters x 1 line/2 lines/3 lines/4 lines HD66727 2.4V to 5.5V 3.0 to 13.0V 12 characters x 1 line/2 lines/3 lines/4 lines
Segment display Display duty ratio CGROM
CGRAM DDRAM SEGRAM Segment signals Common signals Liquid crystal drive waveform Clock source Rf oscillation frequency
40 (and 10 annunciators) 1/10, 1/18, 1/26, and 1/34 9,600 bits (240 5-x-8 dot characters) 32 bytes 60 bytes 8 bytes 60 34 B External resistor or external clock 1-line mode: 40 kHz 30% 2-line mode: 80 kHz 30% 3-line mode: 120 kHz 30% 4-line mode: 160 kHz 30% Double or triple booster circuit Built-in for each V1 to V5 Internal 1/4 and 1/6 bias resistors Incorporated None None Reset input Impossible Dot (raster-row) unit 1, 2, 3, or 4 Standby mode and sleep mode I2C, serial, 4, or 8 bits Slim chip with/without bumps TCP
40 (and 12 annunciators) 1/10, 1/18, 1/26, and 1/34 11,520 bits (240 6-x-8 dot characters) 32 bytes 60 bytes 8 bytes 60 34 B External resistor or external clock 1-line mode: 40 kHz 30% 2-line mode: 80 kHz 30% 3-line mode: 120 kHz 30% 4-line mode: 160 kHz 30% Double or triple booster circuit Built-in for each V1 to V5 Internal 1/4 and 1/6 bias resistors Incorporated 4 x 8 = 32 keys None Reset input Impossible Dot (raster-row) unit 1, 2, 3, or 4 Standby mode and sleep mode I2C or clock-synchronized serial Slim chip with/without bumps TCP
Liquid crystal voltage booster circuit Liquid crystal drive operational amplifier Bleeder-resistor for liquid crystal drive Liquid crystal contrast adjuster Key scan circuit Extension driver control signal Reset function
Double or triple booster circuit None External None
5 x 6 = 30 keys Independent control signal Internal reset circuit or reset input Horizontal smooth scroll Dot unit and line unit Vertical smooth scroll Impossible Number of displayed lines 1 or 2 Low power control Low power mode and sleep mode Bus interface Serial Package 100-pin QFP1420 100-pin TQFP1414 100-pin bare chip
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HD66727
HD66727 Block Diagram
OSC1 OSC2 EXM AGND
CPG RESET* TEST Timing generator ASEG1- ASEG12 Annunciator driver
34-bit bidirectional common shift register
Instruction register (I R) LED0- LED2 PORT0- PORT2 IM LED output port
Instruction decoder
7
ACOM
8
Address counter (AC) 7
Display data RAM (DDRAM) 60 x 8 bits
COM1/32- COM32/1 COMS1/2
Common driver
ID0 ID1/CS* SCL SDA
Serial interface * I2C bus * Clock synchronized serial 4
Busy flag (BF) 8 Data register (DR) 6 3 6 8
8 SEG1/60- SEG60/1
60-bit segment shift register 8
60-bit latch circuit
Segment driver
6
KIN0- KIN3
Key scan registers (SCAN0-SCAN7) Key scan timing controller Segmemt RAM (SGRAM) 8 bytes
KST0- KST7
Character generator RAM (CGRAM) 32 bytes
Character generator ROM (CGROM) 11,520 bits
Cursor and blink controller
LCD drive voltage selector
Vci C1 C2 V5OUT2 V5OUT3 6 6 Double/triple booser
Parallel/serial converter
VCC GND +- R R +- 2R +- R +- R +- VR
OPOFF VREF VREFP VREFM
V1OUT
V2
V2OUT
V3
V3OUT
V4OUT
V5OUT
VEE
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HD66727
HD66727 Pad Coordinates
No. -- 1 2 3 -- -- 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Pad Name DUM1 VCC VCC VCC DUM2 DUM3 V1OUT V2OUT V3OUT V4OUT V5OUT VREFP VREF VREFM V2 V3 VEE VEE V5OUT3 V5OUT3 V5OUT2 V5OUT2 C1 C1 C1 C2 C2 C2 VCI VCI GND GND VCC VCC OSC2 OSC1 EXM OPOFF TEST RESET* IM VCCDUM1 ID0 VCCDUM2 ID1 SCL SDA KIN0 X -5446 -5146 -5022 -4898 -4648 -4524 -4336 -4216 -4095 -3975 -3855 -3734 -3614 -3494 -3373 -3253 -3106 2985 -2829 -2708 -2528 -2407 -2216 -2095 -1975 -1822 -1701 -1580 -1389 -1268 -1083 -962 -792 -672 -459 -315 -148 19 185 352 519 666 789 937 1059 1226 1392 1571 Y No. -1244 -1244 -1244 -1244 -1244 -1244 -1169 -1169 -1169 -1169 -1169 -1169 -1169 -1169 -1169 -1169 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1173 -1173 -1173 -1173 -1173 -1173 -1173 -1173 -1173 -1173 -1173 -1173 -1173 -1173 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 -- 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 -- -- -- -- -- 85 86 87 Pad Name KIN1 KIN2 KIN3 KST0 KST1 KST2 KST3 KST4 KST5 KST6 KST7 IRQ* LED0 LED1 LED2 PORT0 PORT1 PORT2 GND GND GND AGND DUM4 COM16/17 COM15/18 COM14/19 COM13/20 COM12/21 COM11/22 COM10/23 COM9/24 COM8/25 COM7/26 COM6/27 COM5/28 COM4/29 COM3/30 COM2/31 COM1/32 COMS2/S1 DUM5 DUM6 DUM7 DUM8 DUM9 ACOM1 ASEG1 ASEG2 X 1737 1904 2071 2261 2421 2581 2740 2900 3060 3220 3380 3539 3716 3876 4036 4228 4403 4578 4735 4855 5054 5263 5446 5446 5446 5446 5446 5446 5446 5446 5446 5446 5446 5446 5446 5446 5446 5446 5446 5446 5446 5194 5070 4945 4821 4585 4461 4337 Y No. -1173 -1173 -1173 -1173 -1173 -1173 -1173 -1173 88 89 90 91 92 93 94 95 Pad Name ASEG3 ASEG4 ASEG5 ASEG6 ASEG7 ASEG8 ASEG9 ASEG10 ASEG11 ASEG12 SEG1/60 SEG2/59 SEG3/58 SEG4/57 SEG5/56 SEG6/55 SEG7/54 SEG8/53 SEG9/52 SEG10/51 SEG11/50 SEG12/49 SEG13/48 SEG14/47 SEG15/46 SEG16/45 SEG17/44 SEG18/43 SEG19/42 SEG20/41 SEG21/40 SEG22/39 SEG23/38 SEG24/37 SEG25/36 SEG26/35 SEG27/34 SEG28/33 SEG29/32 SEG30/31 SEG31/30 SEG32/29 SEG33/28 SEG34/27 SEG35/26 SEG36/25 SEG37/24 SEG38/23 X 4212 4088 3963 3839 3714 3590 3465 3341 3217 3092 2824 2700 2575 2451 2326 2202 2078 1953 1829 1704 1580 1455 1331 1206 1082 958 833 709 584 460 335 211 87 -38 -162 -287 -411 -536 -660 -785 -909 -1033 -1158 -1282 -1407 -1531 -1656 -1780 Y No. 1191 1191 1191 1191 1191 1191 1191 1191 1191 1191 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 -- -- -- -- -- 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 Pad Name SEG39/22 SEG40/21 SEG41/20 SEG42/19 SEG43/18 SEG44/17 SEG45/16 SEG46/15 SEG47/14 SEG48/13 SEG49/12 SEG50/11 SEG51/10 SEG52/9 SEG53/8 SEG54/7 SEG55/6 SEG56/5 SEG57/4 SEG58/3 SEG59/2 SEG60/1 DUM10 DUM11 DUM12 DUM13 DUM14 COM17/16 COM18/15 COM19/14 COM20/13 COM21/12 COM22/11 COM23/10 COM24/9 COM25/8 COM26/7 COM27/6 COM28/5 COM29/4 COM30/3 COM31/2 COM32/1 COMS1/S2 X -1905 -2029 -2153 -2278 -2402 -2527 -2651 -2776 -2900 -3024 -3149 -3273 -3398 -3522 -3647 -3771 -3896 -4020 -4144 -4269 -4393 -4518 -4773 -4898 -5022 -5146 -5446 -5446 -5446 -5446 -5446 -5446 -5446 -5446 -5446 -5446 -5446 -5446 -5446 -5446 -5446 -5446 -5446 -5446 Y 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1260 1260 1260 1260 1260 970 845 721 596 472 348 223 99 -26 -150 -275 -399 -524 -648 -772 -897 -1021
1173 96 -1173 -1173 -1173 -1173 -1173 -1173 -1173 -1173 -1173 -1201 -1201 -1201 -1201 -1201 -1020 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111
-896 112 -772 113 -647 114 -523 115 -398 116 -274 117 -149 118 -25 119 100 120 224 121 348 122 473 123 597 124 722 125 846 126 971 127 1246 128 1246 129 1246 130 1246 131 1246 132 1191 133 1191 134 1191 135
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HD66727
HD66727 Pad Arrangement
COM17/16 COM18/15 COM19/14 COM20/13 COM21/12 COM22/11 COM23/10 COM24/9 COM25/8 COM26/7 COM27/6 COM28/5 COM29/4 COM30/3 COM31/2 COM32/1 COMS1/S2
Chip size: 11.39 m x 2.89 m Pad coordinates: Pad center Coordinate origin: Chip center Pad pitch: 120 m Al pad size: 90 m x 90 m Au bump size: 70 m x 70 m DUM1 VCC VCC VCC DUM2 DUM3 V1OUT V2OUT V3OUT V4OUT V5OUT VREFP VREF VREFM V2 V3 VEE VEE V5OUT3 V5OUT3 V5OUT2 V5OUT2 C1 C1 C1 C2 C2 C2 Vci Vci GND GND VCC VCC OSC2 OSC1 EXM OPOFF TEST RESET* IM VCCDUM1 ID0 VCCDUM2 ID1/CS* SCL SDA KIN0 KIN1 KIN2 KIN3 KST0 KST1 KST2 KST3 KST4 KST5 KST6 KST7 IRQ* LED0 LED1 LED2 PORT0 PORT1 PORT2 GND GND GND AGND DUM4
HD66727
(TOP view)
Y
X
DUM14 DUM13 DUM12 DUM11 DUM10 SEG60/1 SEG59/2 SEG58/3 SEG57/4 SEG56/5 SEG55/6 SEG54/7 SEG53/8 SEG52/9 SEG51/10 SEG50/11 SEG49/12 SEG48/13 SEG47/14 SEG46/15 SEG45/16 SEG44/17 SEG43/18 SEG42/19 SEG41/20 SEG40/21 SEG39/22 SEG38/23 SEG37/24 SEG36/25 SEG35/26 SEG34/27 SEG33/28 SEG32/29 SEG31/30 SEG30/31 SEG29/32 SEG28/33 SEG27/34 SEG26/35 SEG25/36 SEG24/37 SEG23/38 SEG22/39 SEG21/40 SEG20/41 SEG19/42 SEG18/43 SEG17/44 SEG16/45 SEG15/46 SEG14/47 SEG13/48 SEG12/49 SEG11/50 SEG10/51 SEG9/52 SEG8/53 SEG7/54 SEG6/55 SEG5/56 SEG4/57 SEG3/58 SEG2/59 SEG1/60 ASEG12 ASEG11 ASEG10 ASEG9 ASEG8 ASEG7 ASEG6 ASEG5 ASEG4 ASEG3 ASEG2 ASEG1 ACOM1 DUM9 DUM8 DUM7 DUM6 DUM5
COMS2/S1 COM1/32 COM2/31 COM3/30 COM4/29 COM5/28 COM6/27 COM7/26 COM8/25 COM9/24 COM10/23 COM11/22 COM12/21 COM13/20 COM14/17 COM15/18 COM16/17
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HD66727
Chip-on-Glass (COG) Mounting and Routing Examples
LCD Glass
Dummy VCC VCC VCC Dummy Dummy V1OUT V2OUT V3OUT V4OUT V5OUT
V5OUT3 V5OUT2 C1 C2 VCC
OSC2 OSC1 EXM
OPOFF="GND" TEST="VCC"
VREFP VREF VREFM V2 V3 VEE VEE V5OUT3 V5OUT3 V5OUT2 V5OUT2 C1 C1 C1 C2 C2 C2 Vci Vci GND GND VCC VCC OSC2 OSC1 EXM OPOFF TEST IM Vccdummy ID0 Vccdummy ID1/CS* SCL SDA KIN0 KIN1 KIN2 KIN3 KST0 KST1 KST2 KST3 KST4 KST5 KST6 KST7 IRQ* LED0 LED1 LED2 PORT0 PORT1 PORT2 GND GND AGND Dummy
RESET*
IM="GND" ID0="VCC" ID1="GND"
SCL SDA KIN0 KIN1 KIN2 KIN3 KST0 KST1 KST2 KST3 KST4 KST5 KST6 KST7 IRQ* LED0 LED1 LED2 PORT0 PORT1 PORT2 GND
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HD66727
TCP Dimensions
I/O and power supply
0.60P x (51-1) = 30.0 mm
VCC V1OUT V2OUT V3OUT V4OUT V5OUT VREFP VREF VREFM V2 V3 VEE V5OUT3 V5OUT2 C1 C2 Vci GND VCC OSC2 OSC1 EXM OPOFF TEST RESET* IM ID0 ID1/CS* SCL SDA KIN0 KIN1 KIN2 KIN3 KST0 KST1 KST2 KST3 KST4 KST5 KST6 KST7 IRQ* LED0 LED1 LED2 PORT0 PORT1 PORT2 GND AGND
Dummy COMS1/2 COM32/1
0.60mm pitch
HD66727 HIT ACHI
COM17/16 SEG60/1
0.26 mm pitch
LCD driver outputs
0.26P x (109-1) = 28.08 mm
SEG1/60 ASEG12
ASEG1 ACOMS COMS2/1 COM1/32
COM16/17 Dummy
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HD66727
HD66727 Mounting Variations and Key-Matrix Configurations
(1) COB-1 LCD glass COB board Chip
R C C
(2) COB-2 LCD glass
(3) TCP LCD glass
(4) COG LCD glass
Chip TCP Heat seal Heat seal Chip
R C C R
Chip
Heat seal
C R C C
C
ON
F1
F2
ON
F1
F2
ON
F1
F2
ON
F1
F2
1 4 7
2 5 8 0
3 6 9 #
1 4 7
2 5 8 0
3 6 9 #
1 4 7
2 5 8 0
3 6 9 #
1 4 7
2 5 8 0
3 6 9 #
Key-matrix board
Key-matrix board
Key-matrix board
Key-matrix board
Figure 1 HD66727 Mounting Variations
Table 2
Configurations of LCD Modules (LCM) with Key Scan Function for Different Mounting Methods
Chip-on-Board (COB) Mounting 1 Necessary Necessary Bare chip Necessary Necessary Chip-on-Board (COB) Mounting 2 Necessary Not necessary Bare chip Necessary Necessary Tape-CarrierPackage (TCP) Mounting Necessary Not necessary TCP Optional Necessary Chip-on-Glass (COG) Mounting Necessary Not necessary Bumped chip Necessary Necessary
Parts LCD glass LCM (COB) substrate HD66727 package Heat seal Key matrix substrate
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HD66727
Pin Functions
Table 3
Signal IM
Pin Functional Description
Number of Pins I/O 1 I Connected to VCC or GND Function Selects the MPU interface mode: Low: I2C bus mode High: Clock-synchronized serial mode
ID1/ CS*
1
I
ID1: VCC or GND Inputs the HD66727's identification code (ID1) in the I2C CS*: MPU bus mode. Selects the HD66727 in the clock-synchronized serial mode: Low: HD66727 is selected and can be accessed High: HD66727 is not selected and cannot be accessed MPU Inputs/outputs serial (receive/transmit) data and outputs the acknowledge bit in the I2C bus mode. Inputs/outputs serial (receive/transmit) data in the clocksynchronized serial mode. Inputs serial clock pulses. Serial data is latched at the rising edge of each clock pulse. Inputs the HD66727's identification code in both interface modes; must be fixed to high or low. Generates the key scan interrupt signal. Generates strobe signals for latching scanned data from the key matrix at specific time interval. Samples key state from key matrix synchronously with strobe signals. Output ports for control of LED or back light. Can draw 2 mA-3 mA sink current. Also used as general ports. General output ports. These ports cannot drive current such as LED control. Common output signals for segment-icon display. Common output signals for character display: COM1 to COM8 for the first line; COM9 to COM16 for the second line, COM17 to COM24 for the third line, and COM25 to COM32 for the fourth line. All the unused pins output deselection waveforms. In the sleep mode (SLP = 1) or standby mode (STB = 1), all pins output VCC level. The CMS bit can change the shift direction of the common signal. For example, if CMS = 0, COM1/32 is COM1. If CMS = 1, COM1/32 is COM32.
SDA
1
I/O
SCL ID0 IRQ* KST0- KST7
1 1 1 8
I I O O I O O O O
MPU VCC or GND MPU Key matrix Key matrix LED back light General output LCD LCD
KIN0-KIN3 4 LED0- LED2 PORT0- PORT2 COMS1/2, COMS2/1 3 3 2
COM1/32- 32 COM32/1
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HD66727
Table 3
Signal
Pin Functional Description (cont)
Number of Pins I/O O Connected to LCD Function Segment output signals for segment-icon display and character display. In the sleep mode (SLP = 1) or standby mode (STB = 1), all pins output VCC level. The SGS bit can change the shift direction of the segment signal. For example, if SGS = 0, SEG1/60 is SEG1. If SGS = 1, SEG1/60 is SEG60. Common output signal for annunciator display; can drive display statically between VCC and AGND levels; outputs VCC level while annunciator display is turned off (DA = 0). Segment output signals for annunciator display; can drive display statically between VCC and AGND levels; output V CC level while annunciator display is turned off (DA = 0). V2 and V3 are voltage levels for the internal operational amplifiers; can drive LCD with 1/4 bias when V2 and V3 are short-circuited and with 1/6 bias when they are left disconnected. Adjusts the driving capability of the internal operational amplifiers according to the LCD power suppoly voltage. LCD Power Supply Voltage (VCC-VEE) VCC-VEE: 3V-5V VCC-VEE: 4V-6V VCC-VEE: 5V-8V VCC-VEE: 7V or more Pin Settings VREF, VREFP, and VREFM Only VREF and VREFP shorted All pins open All pins shorted Only VREF and VREFM shorted
SEG1/60- 60 SEG60/1
ACOM
1
O
LCD
ASEG1- ASEG12
12
O
LCD
V2, V3
2
I
Open or shortcircuited
VREFP, VREF, VREFM
3
I
Open or shortcircuited
V1OUT- V5OUT
5
I or O Open or Used for output from the internal operational amplifiers external when they are used (OPOFF = GND); when amplifiers' bleeder-resistor driving capability is insufficient, attach a capacitor to stabilize the output. Especially these capacitors for V1OUT and V4OUT must be attached in 1/26 duty and 1/34 duty. When the amplifiers are not used (OPOFF = VCC), V1 to V5 voltages can be supplied to these pins externally. -- -- -- -- Power supply Power supply Power supply GND power supply for LCD drive. VCC - VEE 13V. VCC: +2.4V to +5.5V; GND (logic): 0V Low level power supply for annunciator display; can adjust contrast of annunciators; AGND GND.
VEE VCC, GND AGND OSC1, OSC2
2 8 1 2
OscillationFor R-C oscillation, connect an external resistor. For resistor or clock external clock supply, input clock pulses to OSC1.
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HD66727
Table 3
Signal Vci
Pin Functional Description (cont)
Number of Pins I/O 2 I Connected to Power supply Function Inputs a reference voltage and supplies power to the booster; generates the liquid crystal display drive voltage from the operating voltage. Vci = 1.0V to 5.0V VCC Voltage input to the Vci pin is boosted twice and output. When the voltage is boosted three times, the same capacitance as that of C1-C2 should be connected here. Voltage input to the Vci pin is boosted three times and output. External capacitance should be connected here when using the booster.
V5OUT2
3
O
VEE pin/booster capacitance
V5OUT3 C1, C2 RESET* EXM
2 6 1 1
O -- I I
VEE pin Booster capacitance
MPU or external Reset pin. Initializes the LSI when low. Be sure to input R-C circuit this signal after power-on. MPU External alternating signal used for annunciator display in the standby mode. If annunciator display is not used, EXM must be fixed to VCC or GND. Turns the internal operational amplifier off when OPOFF = VCC, and turns it on when OPOFF = GND. If the amplifier is turned off (OPOFF = VCC), V1 to V5 must be supplied to the V1OUT to V5OUT pins. Outputs VCC supply level; can fix the input pads to VCC level. Test pin. Must be fixed at GND level.
OPOFF
1
I
VCC or GND
VCC dummy 2 TEST 1
0 I
Input pad GND
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HD66727
Block Function Description
System Interface The HD66727 has two types of system interfaces: I2C bus and clock-synchronized serial. The interface mode is selected by the IM pin. The HD66727 has two 8-bit registers: an instruction register (IR) and a data register (DR). The IR stores instruction codes, such as clear display, return home, and display control, and address information for display data RAM (DDRAM), character generator RAM (CGRAM), and segment RAM (SEGRAM). The IR can only be written to by MPU and cannot be read from. The DR temporarily stores data to be written into DDRAM, CGRAM, SEGRAM, or annunciator. Data written into the DR from the MPU is automatically written into DDRAM, CGRAM, SEGRAM, or annunciator by an internal operation. The DR is also used for data storage when reading data from DDRAM, CGRAM, or SEGRAM. When address information is written into the IR, data is read and then stored into the DR from DDRAM, CGRAM, or SEGRAM by an internal operation. Data transfer between the MPU is then completed when the MPU reads the DR. After the read, data in DDRAM, CGRAM, or SEGRAM at the next address is sent to the DR for the next read from the MPU. These two registers and the operations can be selected by the register select bit (RS) and the read/write bit (R/W) as listed in Table 4. For details, see the Serial Data Transfer section. Table 4
RS Bit 0 0 1 1
Register Selection by RS and R/W Bits
R/W Bit 0 1 0 1 Operation IR write as an internal operation Read busy flag (DB7) and key scan data (DB3 to DB0) DR write as an internal operation (DR to DDRAM, CGRAM, SEGRAM, or annunciator) DR read as an internal operation (DDRAM, CGRAM, or SEGRAM to DR)
Busy Flag (BF) When the busy flag is 1, the HD66727 is in the internal operation mode, and the next instruction will not be accepted. When RS = 0 and R/W = 1, the busy flag is output from DB7. The next instruction must be written after ensuring that the busy flag is 0, or data must be transferred in appropriate timing considering instruction execution times.
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HD66727
Key Scan Registers (SCAN0 to SCAN7) The key matrix scanner senses and holds the key states at each rising edge of the key strobe signals that are output by the HD66727. The key strobe signals are output as time-multiplexed signals from KST0 to KST7. After passing through the key matrix, these strobe signals are used to sample the key status on four inputs KIN0 to KIN3, enabling up to 32 keys to be scanned. The states of inputs KIN0 to KIN3 are sampled by key strobe signal KST0 and latched into register SCAN0. Similarly, the data sampled by strobe signals KST1 to KST7 is latched into registers SCAN1 to SCAN7, respectively. Address Counter (AC) The address counter (AC) assigns addresses to DDRAM, CGRAM, or SEGRAM. When the address set instruction is written into the IR, the address information is sent from the IR to the AC. Selection of DDRAM, CGRAM, and SEGRAM is also determined concurrently by the instruction. Figure 2 shows the address counter and a sample DDRAM address setting to the address counter. After writing into (reading from) DDRAM, CGRAM, or SEGRAM, the AC is automatically incremented by 1 (or decremented by 1).
MSB Address counter (AC) LSB
AC 6 AC5 AC4 AC3 AC2 AC1 AC0
Example : DDRAM address 4A 1 0 0 1 0 1 0
Figure 2 Address Counter and Sample DDRAM Address Setting Display Data RAM (DDRAM) Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its capacity is 60 x 8 bits, or 60 characters, which is equivalent to an area of 12 characters x 5 lines. Any number of display lines (LCD drive duty ratio) from 1 to 4 can be selected by software. Here, assignment of DDRAM addresses is the same for all display modes (Table 5). The line to be displayed at the top of the display (display-start line) can also be selected by register settings. See Table 6.
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HD66727
Table 5
Display Line 1st 2nd 3rd 4th 5th
DDRAM Addresses and Display Positions
1st 2nd 3rd 4th 5th 6th 7th 8th 9th Char. Char. Char. Char. Char. Char. Char. Char. Char. 00 10 20 30 40 01 11 21 31 41 02 12 22 32 42 03 13 23 33 43 04 14 24 34 44 05 15 25 35 45 06 16 26 36 46 07 17 27 37 47 08 18 28 38 48 10th 11th 12th Char. Char. Char. 09 19 29 39 49 0A 1A 2A 3A 4A 0B 1B 2B 3B 4B
Note: Char. indicates character position.
Table 6
Display-Line Modes, Display-Start Line, and DDRAM Addresses
Display-Start Lines
DisplayLine Mode 1-line (NL = 00) 2-line (NL = 01)
Duty Ratio 1/10 1/18
Common Pins COM1- COM8 COM1- COM8 COM9- COM16
1st Line (SN = 000)
2nd Line (SN = 001)
3rd Line (SN = 010)
4th Line (SN = 011)
5th Line (SN = 100)
"00"H-"0B"H "10"H-"1B"H "20"H-"2B"H "30"H-"3B"H "40"H-"4B"H "00"H-"0B"H "10"H-"1B"H "20"H-"2B"H "30"H-"3B"H "40"H-"4B"H "10"H-"1B"H "20"H-"2B"H "30"H-"3B"H "40"H-"4B"H "00"H-"0B"H "00"H-"0B"H "10"H-"1B"H "20"H-"2B"H "30"H-"3B"H "40"H-"4B"H "10"H-"1B"H "20"H-"2B"H "30"H-"3B"H "40"H-"4B"H "00"H-"0B"H "20"H-"2B"H "30"H-"3B"H "40"H-"4B"H "00"H-"0B"H "10"H-"1B"H "00"H-"0B"H "10"H-"1B"H "20"H-"2B"H "30"H-"3B"H "40"H-"4B"H "10"H-"1B"H "20"H-"2B"H "30"H-"3B"H "40"H-"4B"H "00"H-"0B"H "20"H-"2B"H "30"H-"3B"H "40"H-"4B"H "00"H-"0B"H "10"H-"1B"H "30"H-"3B"H "40"H-"4B"H "00"H-"0B"H "10"H-"1B"H "20"H-"2B"H
3-line (NL = 10)
1/26
COM1- COM8 COM9- COM16 COM17- COM24
4-line (NL = 11)
1/34
COM1- COM8 COM9- COM16 COM17- COM24 COM25- COM32
Character Generator ROM (CGROM) Character generator ROM (CGROM) generates 6 x 8-dot character patterns from 8-bit character codes. It can generate 240 6 x 8-dot character patterns. Table 7 illustrates the relation between character codes and character patterns for the Hitachi standard CGROM. User-defined character patterns are also available using a mask-programmed ROM (see the Modifying Character Patterns section).
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HD66727
Table 7
Lower Upper
Relation between Character Codes and Character Patterns (ROM code: A03)
x1 CGRAM (2) x2 CGRAM (3) x3 CGRAM (4) x4 CGRAM (1) x5 CGRAM (2) x6 CGRAM (3) x7 CGRAM (4) x8 CGRAM (1) x9 CGRAM (2) xA CGRAM (3) xB CGRAM (4) xC CGRAM (1) xD CGRAM (2) xE CGRAM (3) xF CGRAM (4)
x0 CGRAM (1)
0y
1y
2y
3y
4y
5y
6y
7y
8y
9y
Ay
By
Cy
Dy
Ey
Fy
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HD66727
Table 7
Lower Upper
Relation between Character Codes and Character Patterns (ROM code: A04)
x1 CGRAM (2) x2 CGRAM (3) x3 CGRAM (4) x4 CGRAM (1) x5 CGRAM (2) x6 CGRAM (3) x7 CGRAM (4) x8 CGRAM (1) x9 CGRAM (2) xA CGRAM (3) xB CGRAM (4) xC CGRAM (1) xD CGRAM (2) xE CGRAM (3) xF CGRAM (4)
x0 CGRAM (1)
0y
1y
2y
3y
4y
5y
6y
7y
8y
9y
Ay
By
Cy
Dy
Ey
Fy
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HD66727
Character Generator RAM (CGRAM) Character generator RAM (CGRAM) of 32 x 6 bits allows the user to redefine the character patterns. In the case of 6 x 8-dot characters, up to four characters may be redefined. Write the character codes at addresses "00"H to "03"H into DDRAM to display the character patterns stored in CGRAM (Table 8). Table 8 Example of Relationships between Character Code (DDRAM) and Character Pattern (CGRAM Data)
CGRAM address A4 A3 0 0 A2 A1 A0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
MSB
Character code (DDRAM data) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 * * 0 0
CGRAM data
LSB
O7
O6
O5 O4 O3 O2 O1 O0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 0
* * (Don't care)
Character pattern (1)
0
0
0
0
*
*
1
1
1
1
* * (Don't care)
001 001 001 010 100 100 100 000
Character pattern (4)
Notes: 1. The lower 2 bits of the character code correspond to the upper two bits of the CGRAM address (2 bits: 4 types). 2. CGRAM address bits 0 to 2 designate the character pattern raster-row position. The 8th rasterrow is the cursor position and its display is formed by a logical OR with the cursor. 3. In the 5-dot font width, the higher three bits of the CGRAM data are invalid; use the lower five bits (O4 to O0). In the 6-dot font width, the higher two bits are invalid. 4. When the upper four bits (bits 7 to 4) of the character code are 0, CGRAM is selected. Bits 3 and 2 of the character code are invalid (*). Therefore, for example, the character codes 00H and 08H correspond to the same CGRAM address. 5. A set bit in the CGRAM data corresponds to display selection, and 0 to non-selection.
Segment RAM (SEGRAM) Segment RAM (SEGRAM) is used to enable control of segments such as icons and marks by the user program. Segments and characters are driven by a multiplexing drive method.
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HD66727
SEGRAM has a capacity of 8 x 6 bits, for controlling the display of a maximum of 40 (48 in the 6-dot font width) icons and marks. While COMS1 and COMS2 outputs are being selected, SEGRAM is read and segments (icons and marks) are displayed by a multiplexing drive method (20 segments each during COMS1 and COMS2 selection). Bits in SEGRAM corresponding to segments to be displayed are directly set by the MPU, regardless of the contents of DDRAM and CGRAM. Tables 9 and 10 illustrate the correspondence between SEGRAM addresses and driver signals. Table 9 Correspondence between Segment Display SEGRAM Addresses (ASEG) and Driver Signals in the 5-Dot Font Width
Segment Signals LSB D7 0 0 0 * D6 * D5 * D4 SEG1, SEG21, SEG41 SEG6, SEG26, SEG46 SEG11, SEG31, SEG51 SEG16, SEG36, SEG56 SEG1, SEG21, SEG41 SEG6, SEG26, SEG46 SEG11, SEG31, SEG51 SEG16, SEG36, SEG56 D3 SEG2, SEG22, SEG42 SEG7, SEG27, SEG47 SEG12, SEG32, SEG52 SEG17, SEG37, SEG57 SEG2, SEG22, SEG42 SEG7, SEG27, SEG47 SEG12, SEG32, SEG52 SEG17, SEG37, SEG57 D2 SEG3, SEG23, SEG43 SEG8, SEG28, SEG48 SEG13, SEG33, SEG53 SEG18, SEG38, SEG58 SEG3, SEG23, SEG43 SEG8, SEG28, SEG48 SEG13, SEG33, SEG53 SEG18, SEG38, SEG58 D1 SEG4, SEG24, SEG44 SEG9, SEG29, SEG49 SEG14, SEG34, SEG54 SEG19, SEG39, SEG59 SEG4, SEG24, SEG44 SEG9, SEG29, SEG49 SEG14, SEG34, SEG54 SEG19, SEG39, SEG59 D0 SEG5, SEG25, SEG45 SEG10, SEG30, SEG50 SEG15, SEG35, SEG55 SEG20, SEG40, SEG60 SEG5, SEG25, SEG45 SEG10, SEG30, SEG50 SEG15, SEG35, SEG55 SEG20, SEG40, SEG60 Common Signal COMS1
ASEG Address MSB 1
1
0
0
1
*
*
*
COMS1
1
0
1
0
*
*
*
COMS1
1
0
1
1
*
*
*
COMS1
1
1
0
0
*
*
*
COMS2
1
1
0
1
*
*
*
COMS2
1
1
1
0
*
*
*
COMS2
1
1
1
1
*
*
*
COMS2
Notes: 1. When the SFT pin is grounded, the SEG1 pin output is connected to the far left of the LCD panel, and when the SFT pin is high, the SEG60 pin output is connected to the far left. 2. SEG1 to SEG20 data is identical to SEG21 to SEG40 and SEG41 to SEG60 data. 3. The lower five bits (D4 to D0) of SEGRAM data determine on or off display of each segment. A segment is selected (turned on) when the corresponding data is 1, and is deselected (turned off) when the corresponding data is 0. The upper three bits (D7 to D5) are invalid.
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HD66727
Table 10 Correspondence between Segment Display SEGRAM Addresses (ASEG) and Driver Signals in the 6-Dot Font Width
Segment Signals LSB D7 0 0 0 * D6 * D5 SEG1, SEG25, SEG49 SEG7, SEG31, SEG55 SEG13, SEG37 SEG19, SEG43 SEG1, SEG25, SEG49 SEG7, SEG31, SEG55 SEG13, SEG37 SEG19, SEG43 D4 SEG2, SEG26, SEG50 SEG8, SEG32, SEG56 SEG14, SEG38 SEG20, SEG44 SEG2, SEG26, SEG50 SEG8, SEG32, SEG56 SEG14, SEG38 SEG20, SEG44 D3 SEG3, SEG27, SEG51 SEG9, SEG33, SEG57 SEG15, SEG39 SEG21, SEG45 SEG3, SEG27, SEG51 SEG9, SEG33, SEG57 SEG15, SEG39 SEG21, SEG45 D2 SEG4, SEG28, SEG52 SEG10, SEG34, SEG58 SEG16, SEG40 SEG22, SEG46 SEG4, SEG28, SEG52 SEG10, SEG34, SEG58 SEG16, SEG40 SEG22, SEG46 D1 SEG5, SEG29, SEG53 SEG11, SEG35, SEG59 SEG17, SEG41 SEG23, SEG47 SEG5, SEG29, SEG53 SEG11, SEG35, SEG59 SEG17, SEG41 SEG23, SEG47 D0 SEG6, SEG30, SEG54 SEG12, SEG36, SEG60 SEG18, SEG42 SEG24, SEG48 SEG6, SEG30, SEG54 SEG12, SEG36, SEG60 SEG18, SEG42 SEG24, SEG48 Common Signal COMS1
ASEG Address MSB 1
1
0
0
1
*
*
COMS1
1 1 1
0 0 1
1 1 0
0 1 0
* * *
* * *
COMS1 COMS1 COMS2
1
1
0
1
*
*
COMS2
1 1
1 1
1 1
0 1
* *
* *
COMS2 COMS2
Notes: 1. When the SFT pin is grounded, the SEG1 pin output is connected to the far left of the LCD panel, and when the SFT pin is high, the SEG60 pin output is connected to the far left. 2. SEG1 to SEG24 data are identical to SEG25 to SEG48 and SEG49 to SEG60 data. 3. The lower six bits (D5 to D0) of SEGRAM data determine on or off display for each segment. A segment is selected (turned on) when the corresponding bit is 1, and is deselected (turned off) when the corresponding bit is 0. The upper two bits (D7 to D6) are invalid.
Timing Generation Circuit The timing generation circuit generates timing signals for the operation of internal circuits such as DDRAM, CGROM, CGRAM, and SEGRAM. RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interfering with each other. Therefore, when writing data to DDRAM, for example, there will be no undesirable interferences, such as flickering, in areas other than the display area. Cursor/Blink Control Circuit The cursor/blink (or white-black inversion) control is used to produce a cursor or a flashing area on the display at a position corresponding to the location stored in the address counter (AC).
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HD66727
For example (Figure 3), when the address counter is 08H, a cursor is displayed at a position corresponding to DDRAM address "08"H.
1 00
2 01
3 02
4 03
5 04
6 05
7 06
8 07
9 08
10 11 09 0A
12 0B
Display position DDRAM address
Cursor position Note: The cursor/blink or white-black inversion control is also active when the address counter indicates the CGRAM or SEGRAM. However, it has no effect on the display.
Figure 3 Cursor Position and DDRAM Address Multiplexing Liquid Crystal Display Driver Circuit The multiplexing liquid crystal display driver circuit consists of 34 common signal drivers (COM1 to COM32, COMS1, COMS2) and 60 segment signal drivers (SEG1 to SEG60). When the number of lines are selected by a program, the required common signal drivers automatically output drive waveforms, while the other common signal drivers continue to output deselection waveforms. Character pattern data is sent serially through a 60-bit shift register and latched when all needed data has arrived. The latched data then enables the segment signal drivers to generate drive waveform outputs. The shift direction of 60-bit data can be changed by the SGS bit. The shift direction of the common driver can also be changed by the CMS bit; select the direction appropriate for the device mounting configuration. When multiplexing drive is not used, or during the standby or sleep mode, all the above common and segment signal drivers output the VCC level, halting display. Annunciator Driver Circuit The static annunciator drivers, which are specially used for displaying icons and marks, consists of 1 common signal driver (ACOM) and 12 segment signal drivers (ASEG1 to ASEG12). Since this driver circuit operates at the logic operating voltage (VCC to AGND), the LCD drive power supply circuit is not necessary, and low-power consumption can be achieved. It is suitable for mark indication during system standby because of its drive capability during the standby and sleep modes. When multiplexing drive is not used, or during the standby or sleep mode, all the above common and segment signal drivers output the VCC level, halting display. Tables 11 to 13 illustratate the correspondence between the annunciator addresses (AAN) and driver signals.
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HD66727
Table 11 Correspondence between Annunciator Display Addresses (AAN) and Driver Signals
Annunciator Segment Signals LSB D7 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 Blink Blink Blink D6 ASEG1 Data ASEG5 Data ASEG9 Data Blink Blink D5 D4 ASEG2 Data ASEG6 Data Blink Blink D3 D2 ASEG3 Data ASEG7 Data Blink Blink D1 D0 ASEG4 Data ASEG8 Data Common Signal ACOM ACOM ACOM ACOM ACOM ACOM
AAN Address MSB 0 0 0 0 0 0
ASEG10 Blink Data
ASEG11 Blink Data
ASEG12 Blink Data
Notes: 1. The annunciator is turned on when the corresponding even bit (data) is 1, and is turned off when 0. 2. The turned-on annunciator blinks when the corresponding odd bit (blink) is 1. Blinking is provided by repeatedly turning on the annunciator for 32 frames and then turning it off for the next 32 frames.
Table 12
Correspondence between LED Driving Port Addresses (AAN) and Driver Signals
LED Driving and General Output Port LSB D7 D6 * D5 Port2 D4 Port1 D3 Port0 D2 LED2 D1 LED1 D0 LED0
AAN Address MSB 0 0 1
1
*
General output port
LED driving port
Notes: 1. The LED bits are inverted and output from each LED pin. If 0 is set, the VCC level is output from the LED pin. If 1 is set, the GND level is output from the LED pin. 2. The port bits output from each port pin. If 0 is set, the GND level is output from the PORT pin. If 1 is set, the V CC level is output from the PORT pin. 3. Current cannot be driven for outputs of the V CC level in LED2-LED0 and the VCC and GND levels in PORT2-PORT0. 4. The upper two bits (D7 and D6) are invalid.
Table 13
Correspondence between SEG/COM Addresses (AAN) and Driver Signals
Shift Direction of SEG/COM Driver LSB D7 D6 * D5 * D4 * D3 * D2 * D1 CMS D0 SGS
AAN Address MSB 0 1 0
0
*
Notes: 1. If CMS = 0, COM1/32 is the first line of the first column, and COM32/1 is the 8th line of the fourth column. If CMS = 1, COM1/32 is the 8th line of the fourth column, and COM32/1 is the first line of the first column. If CMS = 0, COMS1/2 is COMS1, and COMS2/1 is COM2. 2. If SGS = 0, SEG1/60 is SEG1 in the left of the display, and SEG60/1 is SEG60 in the right of the display. If SGS = 1, the shift direction of the SEG is reversed. 3. The upper six bits (D7-D2) are invalid.
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HD66727
LED Output Port The HD66727 includes three LED/back-light driving output ports and three general output ports. These ports can control the LED from the microcomputer through the serial interface. Booster (DC-DC Converter) The booster doubles or triples a voltage input to the Vci pin. With this function, both the internal logic units and LCD drivers can be controlled with a single power supply. Oscillator (OSC) The HD66727 can provide R-C oscillation simply by adding an external oscillation-resistor between the OSC1 and OSC2 pins. The appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. Clock pulses can also be supplied externally. Since R-C oscillation is halted during the standby mode, current consumption can be reduced. V-Pin Voltage Followers A voltage follower for each voltage level (V1 to V5) reduces current consumption by the LCD drive power supply circuit. No external resistors are required because of the internal bleeder-resistor, which generates different levels of LCD drive voltage. The voltage followers can be turned off while multiplexing drive is not being used. Contrast Adjuster The contrast adjuster can adjust LCD contrast by varying LCD drive voltage by software. This function is suitable for selecting appropriate brightness of the LCD or for temperature compensation.
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HD66727
Modifying Character Patterns
Character pattern development procedure
User Start Determine character patterns Create EPROM address data listing Write EPROM EPROM Hitachi Computer processing Create character pattern listing Hitachi
Evaluate character patterns No Yes
OK ?
Art work masking Trial Sample
Sample evaluation No Yes
OK ?
Mass production
Figure 4 Character Pattern Development Procedure
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HD66727
The following operations correspond to the numbers listed in Figure 4: Determine the correspondence between character codes and character patterns. Create a listing indicating the correspondence between EPROM addresses and data. Program the character patterns into an EPROM. Send the EPROM to Hitachi. Computer processing of the EPROM is performed at Hitachi to create a character pattern listing, which is sent to the user. 6. If there are no problems within the character pattern listing, a trial LSI is created at Hitachi and samples are sent to the user for evaluation. When it is confirmed by the user that the character patterns are correctly written, mass production of the LSI will proceed at Hitachi. 1. 2. 3. 4. 5.
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HD66727
Programming Character Patterns This section explains the correspondence between addresses and data used to program character patterns in EPROM. Programming to EPROM: The HD66727 character generator ROM can generate 240 6 x 8-dot character patterns. Table 14 shows correspondence between the EPROM address, data, and the character pattern. Table 14 Example of Correspondence between EPROM Address, Data, and Character Pattern (6 x 8 Dots)
EPROM Address A11 A10 A9 A8 A7 A6 A5 A4 A3 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 Character code A2 A1 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
MSB
Data
LSB
O5 O4 O3 O2 O1 O0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 01 0 0 1 0 0 0 1 1 0 0 0 0 0
010
0
Line position
Notes: 1. EPROM address bits A11 to A4 correspond to a character code. 2. EPROM address bits A2 to A0 specify the line position of the character pattern. EPROM address bit A3 must be set to 0. 3. EPROM data bits O5 to O0 correspond to character pattern data. 4. Areas which are lit (indicated by shading) are stored as 1, and unlit areas as 0. 5. The eighth raster-row is also stored in the CGROM, and must also be programmed. If the eighth raster-row is used for a cursor, this data must all be set to zero. 6. EPROM data bits O7 to O6 are invalid. 0 must be written in all bits.
Handling Unused Character Patterns: 1. EPROM data outside the character pattern area: This is ignored by character generator ROM for display operation so any data is acceptable. 2. EPROM data in CGRAM area: Always fill with zeros. 3. Treatment of unused user patterns in the HD66727 EPROM: According to the user application, these are handled in either of two ways: a. When unused character patterns are not programmed: If an unused character code is written into DDRAM, all its dots are lit, because the EPROM is filled with 1s after it is erased. b. When unused character patterns are programmed as 0s: Nothing is displayed even if unused character codes are written into DDRAM. (This is equivalent to a space.)
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HD66727
Instructions
Outline Only the instruction register (IR) and the data register (DR) of the HD66727 can be controlled by the MPU. Before starting internal operation of the HD66727, control information is temporarily stored in these registers to allow interfacing with various peripheral control devices or MPUs which operate at different speeds. The internal operation of the HD66727 is determined by signals sent from the MPU. These signals, which include register selection bit (RS), read/write bit (R/W), and the data bus (DB0 to DB7), make up the HD66727 instructions. There are four categories of instructions that: * * * * * Control display Control key scan Control power management Set internal RAM addresses Perform data transfer with internal RAM
Normally, instructions that perform data transfer with internal RAM are used the most. However, autoincrementation by 1 (or auto-decrementation by 1) of internal HD66727 RAM addresses after each data write can lighten the program load of the MPU. While an instruction is being executed for internal operation, or during reset, no instruction other than the busy flag/key scan read instruction can be executed. Because the busy flag is set to 1 while an instruction is being executed, check it to make sure it is 0 before sending another instruction from the MPU. If an instruction is sent without checking the busy flag, the time between the first instruction issue and next instruction issue must be longer than the instruction execution time itself. Refer to Table 23 for the list of each instruction execution cycles (clock pulses). The execution time depends on the operating clock frequency (oscillation frequency).
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HD66727
Instruction Description
Busy Flag/Key Scan Read The busy flag/key scan read instruction (Figure 5) reads scan data SD3 to SD0 latched into scan registers SCAN0 to SCAN7, scan cycle state SF1 and SF0, and transfer flag TF, sequentially. It also reads the busy flag (BF) indicating that the system is now internally operating on a previously received instruction. If BF is 1, the internal operation is in progress. The next instruction will not be accepted until BF is cleared to 0. Adjust the data transfer rate so that the last bit of the next instruction is received after BF is cleared to 0.
RS R/W DB7 0 1 DB0
BF SF1 SF0 TF SD3 SD2 SD1 SD0
Figure 5 Busy Flag/Key Scan Read Instruction Clear Display The clear display instruction (Figure 6) writes space code 20H (character pattern for character code 20H must be a blank pattern) into all DDRAM addresses. It then sets DDRAM address 0 into the address counter. It also sets I/D to 1 (increment mode) in the entry mode set instruction.
RS R/W DB7 0 0 0 0 0 0 0 0 0 DB0 1
Figure 6 Clear Display Instruction Return Home The return home instruction (Figure 7) sets DDRAM address 0 into the address counter. The DDRAM contents do not change. The cursor or blinking goes to the top left of the display.
RS R/W DB7 0 0 0 0 0 0 0 0 1 DB0 0
Figure 7 Return Home Instruction
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HD66727
Start Oscillator The start oscillator instruction (Figure 8) re-starts the oscillator from a halt state in the standby mode. After issuing this instruction, wait at least 10 ms for oscillation to become stable before issuing the next instruction. (Refer to the Standby Mode section.)
RS R/W DB7 0 0 0 0 0 0 0 0 1 DB0 1
Figure 8 Start Oscillator Instruction Entry Mode Set The entry mode set instruction (Figure 9) includes the I/D and OSC bits. I/D: Increments (I/D = 1) or decrements (I/D = 0) the DDRAM address by 1 when a character code is written into or read from DDRAM. The cursor or blinking moves to the right when incremented by 1 and to the left when decremented by 1. The same applies to writing and reading of CGRAM and SEGRAM. OSC: Divides the external clock frequency by four (OSC = 1) and uses the resulting clock as an operating clock for all internal operations. The execution time for this instruction and subsequent ones is therefore quadrupled. The execution time of clearing this bit (OSC = 0) is also quadrupled. Note that, the key scan cycle is affected. For details, refer to the Partial-Display-Off Function section.
RS R/W DB7 0 0 0 0 0 0 0 1 DB0 I/D OSC
Figure 9 Entry Mode Set Instruction Cursor Control The cursor control instruction (Figure 10) includes the B/W, C, and B bits. B/W: When B/W is 1, the character at the cursor position is cyclically (every 32 frames) displayed with black-white inversion. C: The cursor is displayed on the 8th raster-row when C is 1. The cursor is displayed using 5 dots in the 8th raster-row for 5 x 8-dot character font, or 6 dots in the 8th raster-row for 6 x 8 dot character font. B: The character indicated by the cursor blinks when B is 1. The blinking is displayed as switching between all black dots and displayed characters every 32 frames. The cursor and blinking can be set to display simultaneously. When LC and B = 1, the blinking is displayed as switching between all white dots and displayed characters. Figure 11 shows cursor control examples.
31
HD66727
RS R/W DB7 0 0 0 0 0 0 1 B/W C DB0
B
Figure 10 Cursor Control Instruction
Alternating display (every 32 frames) i) White-black inverting display example
Alternating display ii) 8th raster-row cursor display ii) Blink display example
Figure 11 Cursor Control Examples Display On/Off Control The display on/off control instruction (Figure 12) includes the D, FW, and LC bits. D: The character display and the segment display for multiplexing icon are on when D is 1. When off, the display data remains in DDRAM or SEGRAM, and can be displayed instantly by setting D to 1. When D is 0, multiplexing LCD drive halts and the display is off with the SEG1 to SEG60 outputs, COM1 to COM32 outputs, and COMS1/2 output set to VCC level and off. Because of this, the HD66727 can control charging current for the LCD with driving. FW: When FW = 0, the font width is 5 dots. When FW = 1, the font width is 6 dots. LC: When LC = 1, a cursor attribute is assigned to the line that contains the address counter (AC) value. Cursor mode can be selected with the B/W, C, and B bits. Refer to the Line-Cursor Display section.
RS R/W DB7 0 0 0 0 0 1 0 D DB0 FW LC
Figure 12 Display On/Off Control Instruction
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HD66727
Power Control The power control instruction (Figure 13) includes the AMP, SLP, and STB bits. AMP: When AMP = 1, each voltage follower for V1 to V5 pins and the booster are turned on. When AMP = 0, current consumption can be reduced while character or segment display controlled by the multiplexing drive method is not being used. SLP: When SLP = 1, the HD66727 enters the sleep mode, where all the internal operations are halted except for the annunciator display function, key scan function, and the R-C oscillator, thus reducing current consumption. For details, refer to the Sleep Mode section. Only the following instructions can be executed during the sleep mode. 1. Annunciator address (AAN) set 2. Annunciator data write 3. LED drive/general output port data write 4. Annunciator display on or off (DA = 1 or 0) 5. Voltage follower on or off (AMP = 1 or 0) 6. Standby mode set (STB = 1) 7. Sleep mode cancel (SLP = 0) 8. Key scan data (SD) read 9. Key scan interrupt generation enable/disable (IRE = 1 or 0) 10. Key scan cycle (KF) set During the sleep mode, the other RAM data and instructions cannot be updated but they are retained. STB: When STB = 1, the HD66727 enters the standby mode, where the device completely stops, halting all the internal operations including the internal R-C oscillator and no external clock pulses are supplied. However, annunciator display alone is available when the alternating signal for annunciator-driving signals is supplied to the EXM pin. When the annunciator display is not needed, make sure to turn off display (DA = 0). Normal key scanning is also halted in the standby mode. However, the HD66727 can detect four key inputs connected with strobe signal KST0, thus generating the key scan interrupt (IRQ*). For details, refer to the Standby Mode section and the Key Scan Interrupt section. Only the following instructions can be executed during the standby mode. 1. 2. 3. 4. 5. 6. 7. 8. Annunciator address (AAN) set Annunciator data write LED drive/general output port data write Annunciator display on or off (DA = 1 or 0) Voltage follower on or off (AMP = 1 or 0) Start oscillator Standby mode cancel (STB = 0) Key scan interrupt generation enable/disable (IRE = 1 or 0)
33
HD66727
During the standby mode, the other RAM data and instructions may be lost; they must be set again after the standby mode is canceled.
RS R/W DB7 0 0 0 0 0 1 DB0 1 AMP SLP STB
Figure 13 Power Control Instruction Display Control The display control instruction (Figure 14) includes the NL and DL bits. NL1, NL0: Designates the number of display lines. This value determines the LCD drive multiplexing duty ratio (Table 15). The address assignment is the same for all display line modes. DL3-DL1: Doubles the height of characters on a specified line. The first, second, or third line is doubled in height when DL1, DL2, or DL3 = 1, respectively. Two lines can be simultaneously doubled in a 4-line display. Refer to the Double-Height Display section.
RS R/W DB7 0 0 0 0 1 DB0 NL1 NL0 DL3 DL2 DL1
Figure 14 Display Control Instruction
Table 15
NL1 0 0 1 1 NL0 0 1 0 1
NL Bits and Display Lines
Number of Display Lines 1 2 3 4 LCD Drive Multiplexing Duty Ratio 1/10 1/18 1/26 1/34
Contrast Control The contrast control instruction (Figure 15) includes the SN and CT bits. SN2: Combined with the SN1 and SN0 bits described in the Scroll Control section to select the top line to be scrolled (display-start line). CT3-CT0: Controls the LCD drive voltage (potential difference between VCC and V5) to adjust contrast (Figure 16 and Table 16). For details, refer to the Contrast Adjuster section.
34
HD66727
RS R/W DB7 0 0 0 1 DB0 0 SN2 CT3 CT2 CT1 CT0
Figure 15 Contrast Control Instruction
HD66727
VCC R V2 R R V3 R R R VR VEE
+ - + - + - + - + -
Figure 16 Contrast Adjuster
Table 16
CT3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
CT Bits and Variable Resistor Value of Contrast Adjuster
CT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Variable Resistor Value (VR) 6.4 x R 6.0 x R 5.6 x R 5.2 x R 4.8 x R 4.4 x R 4.0 x R 3.6 x R 3.2 x R 2.8 x R 2.4 x R 2.0 x R 1.6 x R 1.2 x R 0.8 x R 0.4 x R
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HD66727
Scroll Control The scroll control instruction (Figure 17) includes the SN and SL bits. SN1, SN0: Combined with the SN2 bit described in the Contrast Control section to select the top line to be displayed (display-start line) through the data output from the COM1 pin (Table 17). After first five lines are displayed from the top line, the cycle is repeated and scrolling continues. SL2-SL0: Selects the top raster-row to be displayed (display-start raster-row) in the display-start line specified by SN2 to SN0. Any raster-row from the first to eighth can be selected (Table 18). This function is used to perform vertical smooth scroll together with SN2 to SN0. For details, refer to the Vertical Smooth Scroll section.
RS R/W DB7 0 0 0 1 DB0 1 SN1 SN0 SL2 SL1 SL0
Figure 17 Scroll Control Instruction
Table 17
SN2 0 0 0 0 1
SN Bits and Display-Start Lines
SN1 0 0 1 1 0/1 SN0 0 1 0 1 0/1 Display-Start Line 1st line 2nd line 3rd line 4th line 5th line
Table 18
SL2 0 0 0 0 1 1 1 1
SN Bits and Display-Start Raster-Rows
SL1 0 0 1 1 0 0 1 1 SL0 0 1 0 1 0 1 0 1 Display-Start Raster-Row 1st raster-row 2nd raster-row 3rd raster-row 4th raster-row 5th raster-row 6th raster-row 7th raster-row 8th raster-row
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HD66727
Annunciator/SEGRAM Address Set The annunciator/SEGRAM address set instruction (Figure 18) includes the DA and A (AAN/ASEG) bits. DA: Turns annunciator display on or off. When DA = 1, annunciator display is turned on and driven statically. When DA = 0, annunciator display is turned off with ASEG1 to ASEG10 and ACOM pins held to VCC level. The internal operating clock supply is halted during the standby mode; make sure to turn off display (DA = 0) if the external alternating signal is not supplied. For details, refer to the Segment Display and Annunciator Display section and the Standby Mode section. AAAA: Used for setting the SEGRAM address into the address counter (AC) or for directly setting the annunciator address. The SEGRAM addresses range from 1000H to 1111H (8 addresses), while the annunciator addresses range from 0000H to 0010H (3 addresses). The annunciator address is directly set without using the address counter, and consequently must be updated for each access. The annunciator address can be set even during the sleep and standby modes. Once the SEGRAM address is set, data in the SEGRAM can be accessed consecutively since the address counter is automatically incremented or decremented by one according to the I/D bit setting after each access. The SEGRAM address cannot be set during the sleep or standby mode. AAAA is the address for setting the 0011 LED/general port data; 0100 is the address for setting the SEG/COM shift direction. See 'Annunciator Driver Circuit' for details.
RS R/W DB7 0 0 1 0 0 DA A A A DB0 A
Figure 18 Annunciator/SEGRAM Address Set Instruction
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HD66727
Table 19
Address Annunciator address
Annunciator/LED/SEG/COM Shift Direction/SEGRAM Address Set
A 0 0 0 A 0 0 0 0 1 0 0 0 0 1 1 1 1 A 0 0 1 1 0 0 0 1 1 0 0 1 1 A 0 1 0 1 0 0 1 0 1 0 1 0 1 DB7 ASEG1 ASEG5 ASEG9 * * * * * * * * * * * * * * * * * * * * SEGRAM data in COMS2 side DB6 DB5 ASEG2 ASEG6 ASEG10 DB4 DB3 ASEG3 ASEG7 ASEG11 DB2 DB1 ASEG4 ASEG8 ASEG12 LED1 CMS LED0 SGS DB0
LED port address 0 SEG/COM shift direction address SEGRAM address 0 1 1 1 1 1 1 1 1
PORT2 PORT1 PORT0 LED2 * * * *
SEGRAM data in COMS1 side
CGRAM Address Set The CGRAM address set instruction (Figure 19) includes the A (ACG) bits. AAAAA: Used for setting the CGRAM address into the address counter (AC). The CGRAM addresses range from 00H to 1FH (32 addresses) (Table 19). Once the CGRAM address is set, data in the CGRAM can be accessed consecutively since the address counter is automatically incremented or decremented according to the I/D bit setting after each access. The CGRAM address cannot be set during the sleep or standby mode.
RS R/W DB7 0 0 1 0 1 A A A A DB0 A
Figure 19 CGRAM Address Set Instruction
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HD66727
Table 20 CGRAM Addresses and Character Codes
CGRAM Address "00"H to "07"H "08"H to "0F"H "10"H to "17"H "18"H to "1F"H Character Codes "00"H "01"H "02"H "03"H
Displayed Character 1st character 2nd character 3rd character 4th character
DDRAM Address Set The DDRAM address set instruction (Figure 20) includes the A (ADD), IRE, and KF bits. AAAAAAA: Used for setting the DDRAM address into the address counter (AC). The DDRAM addresses range from "00"H to "4B"H (60 addresses) (Table 21). Once the DDRAM address is set, data in the DDRAM can be accessed consecutively since the address counter is automatically incremented or decremented according to the I/D bit setting after each access. Here, invalid addresses are automatically skipped. The DDRAM address cannot be set during the sleep or standby mode.
RS R/W DB7 0 0 1 1 0 IRE KF1 KF0 A DB0 A Upper bits
0
0
1
1
1
A
A
A
A
A
Lower bits
Figure 20 DDRAM Address Set Instruction
Table 21
DDRAM Addresses and Invalid Addresses
DDRAM Address "00"H to "0B"H "10"H to "1B"H "20"H to "2B"H "30"H to "3B"H "40"H to "4B"H Invalid Addresses "0C"H to "0F"H "1C"H to "1F"H "2C"H to "2F"H "3C"H to "3F"H "4C"H and subsequent addresses
Displayed Line 1st line 2nd line 3rd line 4th line 5th line
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HD66727
IRE: When IRE is 1, the key scan interrupt (IRQ*) generation is enabled. When a key is pressed, the IRQ* pin outputs a low level signal. KF1, KF0: Used for specifying the key scan cycle. Set these bits according to the mechanical characteristics of the keys and the oscillation frequency (Table 22). Table 22
NL1 1 or 2 display lines (NL1=0) 1 or 2 display lines (NL1=0) 1 or 2 display lines (NL1=0) 1 or 2 display lines (NL1=0) 3 or 4 display lines (NL1=1) 3 or 4 display lines (NL1=1) 3 or 4 display lines (NL1=1) 3 or 4 display lines (NL1=1)
KF Bits and Key Scan Cycles
KF1 0 0 1 1 0 0 1 1 KF0 0 1 0 1 0 1 0 1 Key Scan Cycle 160/fosc 320/fosc 640/fosc 1,280/fosc 320/fosc 640/fosc 1,280/fosc 2,560/fosc Key Strobe Width 20/fosc 40/fosc 80/fosc 160/fosc 40/fosc 80/fosc 160/fosc 320/fosc
Note: fosc is the oscillation frequency or external clock frequency.
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HD66727
Write Data to RAM The write data to RAM instruction (Figure 21) writes 8-bit data to annunciator or DDRAM, lower 6-bit data to LED port, SEGRAM or CGRAM, or lower two bits to shift direction change bits of SEG/COM that is selected by the previous specification of the address set instruction (annunciator/LED/SEGRAM address set, CGRAM address set, or DDRAM address set). After a write, the address is automatically incremented or decremented by 1 according to the I/D bit setting in the entry mode set instruction. The annunciator or LED port address is not automatically updated; it must be specifically updated to write data to a different address. During the sleep and standby modes, DDRAM, CGRAM, or SEGRAM cannot be accessed.
RS R/W DB7 1 0 D D D D D D D DB0 D
Figure 21 Write Data to RAM Instruction Read Data from RAM The read data from RAM instruction (Figure 22), reads 8-bit data from DDRAM, or 5-bit data from CGRAM or SEGRAM that is selected by the previous specification of the address set instruction (SEGRAM address set, CGRAM address set, or DDRAM address set). The unused upper three bits of CGRAM or SEGRAM data are read as 000; annunciator data cannot be read. If no address is specified by the address set instruction just before this instruction, the first data read will be invalid. When executing consecutive read instructions, the next data is normally read from the next address. After a read, the address is automatically incremented or decremented by 1 according to the I/D bit setting in the entry mode set instruction.
RS R/W DB7 1 1 D D D D D D D DB0 D
Figure 22 Read Data from RAM Instruction
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HD66727
Table 23 Instruction List
Code
No. KS Instruction R/W RS 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description BF SF TF SD Busy 1 flag/key scan read Clear display 0 Execution Cycle *1
Reads busy flag (BF), key- 0 scan state (SF and TF), and data in key scan registers (SD). 1 Clears entire display and sets address 0 into the address counter. Sets DDRAM address 0 into the address counter. Starts the oscillation standby mode. 310
CL
0
0
0
0
0
0
0
0
CH OS EM
Return home 0 Start oscillator Entry mode set 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 1
1 1 I/D
0 1
5 --
OSC Sets the address update 5 direction after RAM access (I/D), and system clock division (OSC). B Sets black-white inverting cursor (B/W), 8th rasterrow cursor (C), and blink cursor (B). Sets character/segment display on (D), font width (FW), and line-cursor display (LC). 5
CR
Cursor control
0
0
0
0
0
0
1
B/W C
DO
Display 0 on/off control
0
0
0
0
1
0
D
FW
LC
5
PW
Power control
0
0
0
0
0
1
1
AMP SLP STB Turns on LCD power 5 supply (AMP), and sets the sleep mode (SLP) and standby mode (STB).
DC
Display control Contrast control
0
0
0
0
1
NL1 NL0 DL3 DL2 DL1 Sets the number of display 5 lines (NL) and the lines to be doubled in height. SN2 CT Sets the display-start line (SN2) and contrastadjusting value (CT). Sets the display-start line (SN) and display-start raster-row (SL). Turns on the annunciator display (DA) and sets annunciator/SEGRAM address. Sets the initial CGRAM address to the address counter. 5
CN
0
0
0
1
0
SC
Scroll control 0
0
0
1
1
SN1 SN0
SL
5
AS
Annunciator/ 0 SEGRAM address set CGRAM address set 0
0
1
0
0
DA
AAN/ASEG
5
CA
0
1
0
1
ACG
5
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HD66727
Table 23 Instruction List (cont)
Code
No. DA Instruction DDRAM address set (upper bits) DDRAM address set (lower bits) R/W RS 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description 1 1 0 IRE KF1 KF0 ADD (upper bits) Sets the initial higher DDRAM address to the address counter, and key scan cycle. Sets the initial lower DDRAM address to the address counter. Writes data to DDRAM, Execution Cycle *1 5
DA
0
0
1
1
1
ADD (lower bits)
5
WD
Write data to 0 RAM
1
Write data
5
CGRAM, SEGRAM, annunciator/LED/gener al port, or SEG/COM shift direction.
1 Read data Reads data from DDRAM, 5 CGRAM, or SEGRAM.
RD
Read data from RAM
1
1. Represented by the number of operating clock pulses; the execution time depends on the supplied clock frequency or the internal oscillation frequency. Bit definition: BF = 1: Internally operating SF: Key-scan state TF = 1: Key-scan internally operating SD: Key-scanned data I/D = 1: Address increment I/D = 0: Address decrement OSC = 1: System clock divided by four B/W = 1: Black-white inverting cursor on C = 1: 8th raster-row cursor on B = 1: Blink cursor on D = 1: Character/segment display on FW = 0: 5-dot font width FW = 1: 6-dot font width LC = 1: Line containing AC given cursor attribute AMP = 1: Voltage followers and booster on SLP = 1: Sleep mode STB = 1: Standby mode CT: Contrast adjustment NL1, NL0: Number of display lines [00: 1 line (1/10 duty ratio), 01: 2 lines (1/18 duty ratio), 10: 3 lines (1/26 duty ratio), 11: 4 lines (1/34 duty ratio)] DL3-DL1: Double-height lines (DL1 = 1: 1st line, DL2 = 1: 2nd line, DL3 = 1: 3rd line) SN2-SN0: Display-start line (000: 1st line, 001: 2nd line, 010: 3rd line, 011: 4th line, 100: 5th line) SL2-SL0: Display-start raster-row (000: 1st raster-row ... 111: 8th raster-row) DA = 1: Annunciator display on AAN/ASEG: Annunciator address (0000-0010), LED/general port address (PORT2-PORT0, LED2-LED0) (0011) AAN/ASEG: SEG/COM shift change address (CMS, SGS) (0100), SEGRAM address (1000-1111)
Note:
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HD66727
ACG: ADD: IRE = 1: KF1, KF0: CGRAM address (00000-11111) DDRAM address (0000000-1001011) Key scan interrupt generation enabled Key scan cycle set
Reset Function
Initialization by Internal Reset Circuit The HD66727 is internally initialized by RESET* input. During initialization, the system executes the instructions as described below. Here, the busy flag (BF) therefore indicates a busy state (BF = 1), accepting no instruction or RAM data access from the MPU. Here, reset input must be held at least 10 ms. After releasing power-on reset, clear display instruction is operated. So wait for 1,000 clock-cycles or more. Make sure to reset the HD66727 immediately after power-on. Initialization of Instruction Sets, RAM, and Pins Instruction set initialization: 1. Clear display executed Writes 20H to DDRAM after releasing reset. 2. Return home executed Sets the address counter (AC) to 00H to select DDRAM 3. Start oscillator executed 4. Entry mode set I/D = 1: Increment by 1 OSC = 0: Clock frequency not divided 5. Cursor control B/W = 0: White-black inverting cursor off C = 0: 8th raster-row cursor off B = 0: Blink cursor off 6. Display on/off control D = 0: Character/segment display off FW = 0: 5-dot font width LC = 0: Line-cursor off 7. Power control AMP = 0: LCD power supply off SLP = 0: Sleep mode off STB = 0: Standby mode off
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HD66727
8. Display control NL1, NL0 = 11: 4-line display (1/34 multiplexing duty ratio) DL3-DL1 = 000: Double-height display off 9. Contrast adjust CT = 0000: Weak contrast 10. Scroll control SN2-SN0 = 000: First line displayed at the top SL2-SL0 = 000: First raster-row displayed at the top of the first line 11. Annunciator control DA = 0: Annunciator display off 12. Key scan control IRE = 0: Key scan interrupt (IRQ*) generation disabled KF1, KF0 = 00: Key scan cycle set to 320 clock cycles 13. LED/general port LED2/LED1/LED0 = 000: LED2/LED1/LED0 outputs = VCC level PORT2/ PORT1/ PORT0 = 000: PORT2/ PORT1/ PORT0 outputs = GND level 14. LCD driver output direction CMS = 0: Starts shift from COM1/32 SGS = 0: Starts shift from SEG1/60 RAM data initialization: 1. DDRAM All addresses are initialized to 20H by the clear display instruction 2. CGRAM/SEGRAM Not automatically initialized by reset input; must be initialized by software while display is off (D = 0) 3. Annunciator data Not automatically initialized by reset input; must be initialized by software while display is off (DA= 0) Output pin initialization: 1. 2. 3. 4. 5. 6. 7. LCD driver output pins (SEG/COM, ASEG/ACOM): Outputs VCC level Booster output pins (V5OUT2 and V5OUT3): Outputs GND level Oscillator output pin (OSC2): Outputs oscillation signal Key strobe pins (KST0 to KST7): Outputs strobe signals at a specified time interval Key scan interrupt pin (IRQ*): Outputs VCC level LED driving port (LED0-LED2): Outputs VCC level General output port (PORT0-PORT2): Outputs GND level
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HD66727
Serial Data Transfer
I2C Bus Interface Grounding the IM pin (interface mode pin) allows serial data transfer conforming to the I 2C bus interface using the serial data line (SDA) and serial transfer clock line (SCL). Here, the HD66727 operates in an transmit/receive slave mode. The HD66727 initiates serial data transfer by transferring the first byte when a high SCL level at the falling edge of the SDA input is sampled; it ends serial data transfer when a high SCL level at the rising edge of the SDA input is sampled. Table 24 illustrates the first bytes of I 2C bus interface data and Figure 23 shows the I2C bus interface timing sequence. The HD66727 is selected when the higher six bits of the 7-bit slave address in the first byte transferred from the master device match the 6-bit device identification code assigned to the HD66727. The HD66727, when selected, receives the subsequent data string. The lower bits of the identification code can be determined by the ID1 and ID0 pins; select an appropriate code that is not assigned to any other slave device. The upper four bits is fixed to 0111. Two different slave addresses must be assigned to a single HD66727 because the least significant bit (LSB) of the slave address is used as a register select bit (RS): when RS = 0, an instruction can be issued or key scan data can be read, and when RS = 1, data can be written to or read from RAM. Read or write is selected according to the eighth bit of the first byte (R/W bit) as shown in Table 25. The ninth bit of the first byte is a receive-data acknowledge bit (ACK). When the received slave address matches the device ID code, the HD66727 pulls down the ACK bit to a low level. Therefore, the ACK output buffer is an open-drain structure, only allowing low-level output. However, the ACK bit is undetermined immediately after power-on; make sure to initialize the LSI using the RESET* input. After identifying the address in the first byte, the HD66727 receives the subsequent data as an HD66727 instruction or as RAM data, or transmits key scan data or RAM data. Having received or transmitted 8-bit data normally, the HD66727 pulls down the ninth bit (ACK) to a low level. Therefore, if the ACK is not returned, the data must be transferred again. Multiple bytes of data can be consecutively transferred until the transfer-end condition is satisfied. Here, when the serial data transfer rate is longer than the HD66727 instruction execution time, effective data transfer is possible without retransmission (see Table 23, Instruction List). Note that the display clear instruction alone requires longer execution time than the others.
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HD66727
Table 24 First Bytes of I 2C Bus Interface Data
Transferred Bit String First Byte of I C bus system * HD66727 *2
2 1
S Transfer start Transfer start
Bit 1 A6 0
Bit 2 A5 1
Bit 3 A4 1
Bit 4 A3 1
Bit 5 A2 ID1
Bit 6 A1 ID0
Bit 7 A0 RS
Bit 8 R/W R/W
Bit 9 ACK ACK
Notes: 1. Bits 1 to 7 of the first byte of the I 2C bus system indicate the I2C slave address. 2. Bits 1 to 6 of the first byte of the HD66727 indicate the device ID code.
Table 25
RS 0 0 1 1 R/W 0 1 0 1
RS and R/W Bit Function of I2C Bus Interface Data
Function Writes instruction Reads key scan data and BF flag Writes RAM data Reads RAM data
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HD66727
a) Basic Data-Receive Timing through the I2C Bus Interface Transfer start 1 SCL (Input) MSB SDA (Input/ output) 0 MSB 1 1 1 ID1 ID0 RS 0 Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack Device ID code Slave address 1st byte Acknowledge RS R/ W 1st instruction 2nd instruction Acknowledge Instructions 2 3 4 5 6 7 8 9 Transfer end 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Acknowledge
b) Basic Data-Transmit Timing through the I2C Bus Interface Transfer start 1 SCL (Input) MSB SDA (Input/ output) 0 MSB 1 1 1 ID1 ID0 RS 1 Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack Device ID code Slave address 1st byte Acknowledge RS R/ W 1st read Acknowledge Instructions 2nd read 2 3 4 5 6 7 8 9 Transfer end 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Acknowledge
c) Consecutive Instruction-Receive Timing through the I2C Bus Interface SCL (Input) SDA (Input/ output) S Start 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
1st byte
A C K
Instruction 1
A C K
Instruction 2 Instruction 1 execution time
A Instruction 3 C K Instruction 2 execution time
A C K
P End
Transfers the instruction-2 ACK after instruction 1 has been executed. d) Consecutive Key-Scanned Data-Transmit Timing through the I2C Bus Interface SCL (Input) SDA (Input/ output) S Start 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
1st byte
A C K
Key-scanned data (SCAN0)
A C K
Key-scanned data (SCAN1)
A C K
Key-scanned data (SCAN2)
A C K
P End
Transfers the ACK after 8-bit data has been transmitted.
e) Consecutive RAM Data-Transmit Timing through the I2C Bus Interface SCL (Input) SDA (Input/ output) S Start 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
1st byte
A C K
RAM data 1
A C K
RAM data 2 RAM data 1 execution time
A C K
RAM data 3
A C K
P End
RAM data 2 execution time
Transfers the RAM data-2 ACK after the RAM data 1 has been executed.
Figure 23
I2C Bus Interface Timing Sequence
48
HD66727
Clock-Synchronized Serial Interface Setting the IM pin (interface mode pin) to the high level allows standard clock-synchronized serial data transfer, using the chip select line (CS*), serial data line (SDA), and serial transfer clock line (SCL). The HD66727 initiates serial data transfer by transferring the start byte at the falling edge of the CS* input. It ends serial data transfer at the rising edge of the CS* input. Table 24 illustrates the first bytes of I2C bus interface data and Figure 24 shows the clock-synchronized serial interface timing sequence. The HD66727 is selected when the 6-bit chip address in the start byte transferred from the transmitting device matches the 6-bit device identification code assigned to the HD66727. The HD66727, when selected, receives the subsequent data string. The least significant bit of the identification code can be determined by the ID0 pin. The upper five bits must be 01110. Two different chip addresses must be assigned to a single HD66727 because the seventh bit of the start byte is used as a register select bit (RS): when RS = 0, an instruction can be issued or key scan data can be read, and when RS = 1, data can be written to or read from RAM. Read or write is selected according to the eighth bit of the start byte (R/W bit) as shown in Table 27. After receiving the start byte, the HD66727 receives or transmits the subsequent data byte-by-byte. Data is transferred with the MSB first. To transfer data consecutively, adjust the data transfer rate so that the HD66727 can complete the current instruction before the eighth bit of the next instruction is transferred (see Table 23, Instruction List). If the next instruction is transferred during execution of the current instruction, the next instruction will be ignored. Note that the display-clear instruction alone requires longer execution time than the others. Table 26
S Transfer start
Start Byte of Clock-Synchronized Serial Interface Data
Bit 1 0 Bit 2 1 Bit 3 1 Bit 4 1 Bit 5 0 Bit 6 ID0 Bit 7 RS Bit 8 R/W
Note: Bits 1 to 6 indicate the device ID code.
Table 27
RS 0 0 1 1 R/W 0 1 0 1
RS and R/W Bit Function of Clock-Synchronized Serial Interface Data
Function Writes instruction Reads key scan data and BF flag Writes RAM data Reads RAM data
49
HD66727
a) Basic Data-Transfer Timing through Clock-Synchronized Serial Bus Interface Transfer start CS* (Input) SCL (Input) SDA (Input/ Output) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Transfer end
MSB
LSB
"0" "1" "1" "1" "0" ID0 RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Device ID code Start byte RS R/W Instruction, RAM data, key-scanned data
b) Consecutive Data-Transfer Timing through Clock-Synchronized Serial Bus Interface CS* (Input) SCL (Input) SDA (Input/ output) Start 12345678 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Start byte
Instruction 1
Instruction 2 Instruction 1 execution time
Instruction 3 Instruction 2 execution time End
Adjust the transfer rate so that the HD66727 can complete instruction 1 before the 8th bit of instruction 2 is transferred.
Figure 24 Clock-Synchronized Serial Interface Timing Sequence
50
HD66727
Key Scan Control
Key Scan Mechanism The key matrix scanner senses and holds the key states at each rising edge of the key strobe signals (KST) that are output by the HD66727. The key strobe signals are output as time-multiplexed signals from KST0 to KST7. After passing through the key matrix, these strobe signals are used to sample the key state on four inputs KIN0 to KIN3, enabling up to 32 keys to be scanned (Figure 25). The states of inputs KIN0 to KIN3 are sampled by key strobe signal KST0 and latched into the SCAN0 register. Similarly, the data sampled by strobe signals KST1 to KST7 is latched into the SCAN1 to SCAN7 registers, respectively (Figure 26). Key pressing is stored as 1 in these registers. The generation cycle and pulse width of the key strobe signals depend on the operating frequency (oscillation frequency) of the HD66727, the display line determined by the NL1 bit, and the key scan cycle determined by the KF0 and KF1 bits. For example, when the operating frequency is 160 kHz, NL1 is 1, and KF0 and KF1 are both 0, the generation cycle is 8.0 ms and the pulse width is 1.0 ms (Figure 27). When the operating frequency (oscillation frequency) is changed, the above generation cycle and the pulse width are also changed in inverse proportion (Table 28).
Key matrix
Detail
D03 D02 D01 D00 D13 D12 D11 D10 D23 D22 D21 D20 D33 D32 D31 D30 D43 D42 D41 D40 D53 D52 D51 D50 D63 D62 D61 D60 D73 D72 D71 D70
KST0 KST1 KST2 KST3 KST4 KST5 KST6 KST7
KIN0 KIN1 KIN2 KIN3
Key strobe
HD66727
Key state input Figure 25 Key Scan Configuration
51
HD66727
KIN3 KIN2 KIN1 KIN0 SCAN0 D03 SCAN1 D13 SCAN2 D23 SCAN3 D33 SCAN4 D43 SCAN5 D53 SCAN6 D63 SCAN7 D73 D02 D01 D12 D11 D22 D21 D32 D31 D42 D41 D52 D51 D62 D61 D72 D71 D00 D10 D20 D30 D40 D50 D60 D70 (KST0 (KST1 (KST2 (KST3 (KST4 (KST5 (KST6 (KST7 ) ) ) ) ) ) ) )
Figure 26 Key Scan Register Configuration
Key scan cycle 8.0 ms 1.0 ms KST0 KST1 KST2 KST3 KST4 KST5 KST6 KST7
Figure 27 Key Strobe Output Timing (NL1 = 1, KF1/0 = 10, fcp/fosc = 160 kHz)
52
HD66727
Table 28
Register NL1 0 (1, 2 lines) 0 (1, 2 lines) 0 (1, 2 lines) 0 (1, 2 lines) 1 (3, 4 lines) 1 (3, 4 lines) 1 (3, 4 lines) 1 (3, 4 lines) KF1 0 0 1 1 0 0 1 1 KF0 0 1 0 1 0 1 0 1
Key Scan Cycles for Each Operating Frequency
Key Scan Cycle Clock Cycle 160 320 640 1,280 320 640 1,280 2,560 160 kHz (1.0 ms)* (2.0 ms)* (4.0 ms)* (8.0 ms)* 2.0 ms 4.0 ms 8.0 ms 16.0 ms 120 kHz (1.3 ms)* (2.7 ms)* (5.3 ms)* (10.7 ms)* 2.7 ms 5.3 ms 10.7 ms 21.3 ms 80 kHz 2.0 ms 4.0 ms 8.0 ms 16.0 ms (4.0 ms)* (8.0ms)* (16.0 ms)* (32.0 ms)* 40 kHz 4.0 ms 8.0 ms 16.0 ms 32.0 ms (8.0ms)* (16.0ms)* (32.0ms)* (64.0ms)*
Note: * Reference value
In order to compensate for the mechanical features of the keys, such as chattering and noise and for the key-strobe generation cycle and the pulse width of the HD66727, software should read the scanned data two or three times in succession to obtain valid data. Multiple keypress combinations should also be processed in software. Up to three keys can be pressed simultaneously. Note, however, that if the third key is pressed on an intersection between the rows and columns of the first two keys pressed, incorrect data will be sampled. For three-key input, the third key must be on a separate column and row. The input pins KIN0 to KIN3 are pulled up to VCC with internal MOS transistors (see the Electrical Characteristics section). External resistors may also be required to further pull up the voltages when the internal pull-ups are insufficient for the desired noise margins or for a large key matrix. Key Scan Data Transfer The key-scanned data can be read by an MPU via a serial interface as shown in Figure 28. First, a start byte should be transferred. After the HD66727 has received the start byte, the MPU reads scan data SD0 to SD3 from the SCAN0 register starting from the MSB. Similarly, the MPU reads data from SCAN1, SCAN2, SCAN3, SCAN4, SCAN5, SCAN6, and SCAN7 in that order. After reading SCAN7, the MPU starts at SCAN0 again. While reading the scanned data, the MPU also reads the scan flags (SF1 and SF0) and the transfer flag (TF). The scan flags reflect the value of the scan cycle counter, which automatically increments its value by one for each scan cycle from 00 to 11 (after 11, it is reset to 00). If the scan data is read more than once to be confirmed, and the corresponding scan counter values are the same, the scan data might have been erroneously latched into the scan register at the same timing; it should be reconfirmed as required. Also, if the transfer flag is read as 1, the HD66727 has been read out while it is latching scan data and is thus unstable; it should also be reconfirmed as required.
53
HD66727
a) Scan Data Read Timing through Clock-Synchronized Serial Bus Interface
Transfer start Transfer end
CS* (Input) SCL (Input) SDA (Input/ output)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0
1
1
1
0 ID0
RS R/W BF SF1 SF0 TF SD3 SD2 SD1 SD0
RS R/W Busy Scan flag Scan data
Device ID code
Start byte
SCAN0 data transmission
b) Scan Data Read Timing through I2C Bus Interface
Transfer start 1 Transfer end 17 18
SCL (Input) SDA (Input/ output)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
1
1
1
ID1 ID0 RS R/W Ack BF SF1 SF0 TF SD3 SD2 SD1 SD0 Ack
RS R/W Busy Scan flag Scan data
Device ID code
1st byte
Acknowledge
SCAN0 data transmission
Acknowledge
c) Consecutive Scan Data Read Timing
Wait Wait Wait Wait Wait
SCL (Input) SDA (Input/ output)
Start byte SCAN0 data
SCAN1 data
SCAN2 data
SCAN3 data
SCAN7 data
SCAN0 data
Figure 28 Scan Data Serial Transfer Timing
54
HD66727
Key Scan Interrupt (Wake-Up Function) If the interrupt enable bit (IRE) is set to 1, the HD66727 sends an interrupt signal to the MPU on detecting that a key has been pressed in the key scan circuit by setting the IRQ* output pin to a low level. An interrupt signal can be generated by pressing any key in a 32-key matrix. The interrupt level continues to be output during the key scan cycle in which the key is being pressed. See Figure 29. Normal key scanning is performed and interrupts can occur in the HD66727 sleep mode (SLP = 1). Accordingly, power consumption can be minimized in the sleep mode, where only annunciators can be displayed, by triggering the MPU to read key states via the interrupt generated only when the HD66727 detects a key input from the 32-key matrix. For details, refer to the Sleep Mode section. On the other hand, normal key scanning and the internal operating clock are halted in the standby mode (STB = 1). During this period, the KST0 output is kept low, so the HD66727 can always sense four key inputs D00 to D03, connected with KIN0 to KIN3, respectively. Therefore, if any of the four keys is pressed in the standby mode, an interrupt occurs. Accordingly, power consumption can be further minimized in the standby mode, where the whole system is inactive, by triggering the MPU via the interrupt generated only when the HD66727 detects a key input from the above four keys. Note that the interrupt generated in the standby mode automatically starts internal R-C oscillation. For details, refer to the Standby Mode section. The IRQ* output pin is pulled up to the VCC with an internal MOS resistor of approximately 50 k; additional external resistors may be required to obtain stronger pull-ups. Interrupts may occur if noise occurs in KIN input during key scanning. Interrupts must be inhibited if not needed by setting the interrupt enable bit (IRE) to 0. Figure 30 shows key scan interrupt processing flow in sleep and standby modes.
VCC HD66727 IRQ* MPU
IRQ*
Interrupt generated
Figure 29 Interrupt Generation
55
HD66727
Turn off LCD power (AMP = 0) Enable interrupts (IRE = 1) Set sleep mode (SLP = 1) Turn off LCD power (AMP = 0) Set standby mode (STB = 1)
Standby mode Enable interrupts (IRE = 1) Key input (key HD66727) Generate interrupt (HD66727 MPU) Start R-C oscillator (HD66727) Wait 10 ms or longer (MPU) Mask interrupts (IRE = 0)
Sleep mode Key input (key HD66727) Generate interrupt (HD66727 MPU) Mask interrupts (IRE = 0) Read key-scanned data
(1) Sleep Mode Clear standby mode (STB = 0) Read key-scanned data
(2) Standby Mode
Figure 30 Key Scan Interrupt Processing Flow in Sleep and Standby Modes
56
HD66727
Oscillator Circuit
The HD66727 can either be supplied with operating clock pulses externally (external clock mode) or oscillate using an internal R-C oscillator and an external oscillator-resistor (internal oscillation mode), as shown in Figure 31. An appropriate oscillator-resistor must be used to obtain the optimum clock frequency according to the number of display lines (Table 29). Instruction execution times change in proportion to the operating clock frequency or R-C oscillation frequency; MPU data transfer rate must be appropriately adjusted (see Table 23, Instruction List). Figure 32 shows a sample LCD drive output waveform, where 4lines are displayed with 1/34 multiplexing duty ratio.
1) When an external clock is used 2) When an internal oscillator is used
Clock
OSC1
Rf
OSC1 OSC2
HD66727
HD66727
The oscillator frequency can be adjusted by oscillator resistance (Rf). If Rf is increased or power supply voltage is decreased, the oscillator frequency decreases.
Figure 31 Oscillator Circuit
Table 29
Item
Oscillation Frequency and LCD Frame Frequency
1-Line Display (NL1, NL0 = 00) 1/10 40 kHz 2-Line Display (NL1, NL0 = 01) 1/18 80 kHz 3-Line Display (NL1, NL0 = 10) 1/26 120 kHz 4-Line Display (NL1, NL0 = 11) 1/34 160 kHz
Multiplexing duty ratio R-C oscillation frequency (recommended value) 1-line drive frequency Frame frequency
0.66 kHz 67 Hz
1.3 kHz 74 Hz
2.0 kHz 77 Hz
2.7 kHz 78 Hz
57
HD66727
1-line selection period 1 VCC V1 COM1 V4 V5 VCC V1 COM2 V4 V5 VCC V1 COMS2 V4 V5 VCC V1 COMS1 V4 V5 1 frame 1 frame 2 3 4 33 34 1 2 3 33 34
Figure 32 LCD Drive Output Waveform Example (4-line display with 1/34 multiplexing duty ratio)
58
HD66727
Power Supply for Liquid Crystal Display Drive
When External Power Supply and Internal Operational Amplifiers are Used To supply LCD drive voltage directly from the external power supply without using the internal booster, circuits should be connected as shown in Figure 33. Here, contrast can be adjusted through the CT bits of the contrast control instruction. The HD66727 incorporates a voltage-follower operational amplifier for each of V1 to V5 to reduce current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal drive voltages. Thus, potential differences between VCC and V1 and between V EE and V5 must be 0.4V or greater. Note that the OPOFF pin must be grounded when using the operational amplifiers.
59
HD66727
OPOFF = GND HD66727 R V2 Open V3 R R R R R VR V EE VEE AGND LCD static driver ASEG1-ASEG12 ACOM + + V1 V2 LCD multiplexing driver COM1-COM32 COMS1-COMS2 V5
VCC
VCC
SEG1-SEG60
+ + + -
V3 V4
GND
a) 3- or 4-line display with 1/6 bias
OPOFF = GND VCC R V2 Short-circuited V3 R R R R R VR V EE VEE AGND LCD static driver ASEG1-ASEG12 ACOM + + + + + HD66727 V1 V2 LCD multiplexing driver COM1-COM16 V4 V5 COMS1-COMS2
VCC
SEG1-SEG60
V3
GND
b) 1- or 2-line display with 1/4 bias
Notes: 1. Potential differences between VCC and V1 and between V5 and VEE must be 0.4V or greater, particularly for low-duty drive such as 1-line display. 2. When the internal operational amplifiers cannot fully drive the LCD panel used, an appropriate capacitor must be inserted between each output of V1OUT to V5OUT and VCC to stabilize the operational amplifier output.
Figure 33 External Power Supply Circuit Example for LCD Drive Voltage Generation
60
HD66727
When an Internal Booster and Internal Operational Amplifiers are Used To supply LCD drive voltage using the internal booster, circuits should be connected as shown in Figure 34. Here, contrast can be adjusted through the CT bits of the contrast control instruction. Temperature can be compensated either through the CT bits or by controlling the reference voltage for the booster (Vci pin) using a thermistor. Note that Vci is both a reference voltage and power supply for the booster; the reference voltage must therefore be adjusted using an emitter-follower or a similar element so that sufficient current can be supplied. In this case, Vci must be equal to or smaller than the V CC level. The HD66727 incorporates a voltage-follower operational amplifier for each of V1 to V5 to reduce current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal drive voltages. Thus, potential differences between VCC and V1 and between V EE and V5 must be 0.4V or greater. Note that the OPOFF pin must be grounded when using the operational amplifiers.
61
HD66727
a) Double boosting OPOFF = GND VCC b) Triple boosting OPOF = GND VCC
VCC
HD66727
R + + - + + - + + - + + - + + - V1 V2
VCC
HD66727
R
+ - + -
V1 V2
V2 Short-circuited for 1-or 2-line display
R R
V2 Short-circuited for 1-or 2-line display
R R
V3
R R R VR
V3 V4 V5
V3
R R R VR
+ - + - + -
V3 V4 V5
VEE Vci C1 0.47 F to 1 F + C2 Booster 0.47 F to 1 F + GND + GND V5OUT2 + V5OUT3 GND
VEE Vci C1 0.47 F C2 to 1 F + V5OUT2 0.47 F to 1 F V5OUT3 Booster
Notes: 1. The reference voltage input (Vci) must be adjusted so that the output voltage after boosting will not exceed the absolute maximum rating of the liquid-crystal power supply voltage (15V). Particularly, Vci must be 5V or less for triple boosting. 2. Vci is both a reference voltage and power supply for the booster; connect it to VCC directly or combine it with a transistor so that sufficient current can be obtained. 3. Vci must be smaller than VCC. 4. To operate the voltage-follower correctly, potential differences between VCC and V1 and between V5 and VEE must be 0.4V or greater, particularly for low-duty drive such as 1-line display. 5. Polarized capacitors must be connected correclty. 6. Circuits for temperature compensation should be designed based on the sample circuit shown in figure 35. 7. The HD66727's internal operational amplifiers have a reduced drive current to save current consumption; when the internal operational amplifiers cannot fully drive the LCD panel used, an appropriate capacitor must be inserted between each output of V1OUT to V5OUT and VCC to stabilize the operational amplifier output (Figure 36).
Figure 34 Internal Power Supply Circuit Example for LCD Drive Voltage Generation
HD66727 VCC VCC
Thermistor
Tr
Vci
GND
Figure 35 Temperature Compensation Circuit Example
62
HD66727
Example of Using Internal Operational Amplifier when Driving Large Size of LCD The driving current of the internal operational amplifier in the HD66727 is reduced to control the consumption current. When load current is apparently large such as when driving large size of LCD panel, insert a capacitor between V1OUT-V5OUT outputs and VCC power supply, and stabilize the output level of the operational amplifier. Especially the capacitors for V1OUT and V4OUT must be inserted when 1/26 duty or 1/34 duty drives.
OPOFF = GND 0.1F to 0.5F* VCC VCC +++++ V1OUT V2 V2OUT R
+ -
HD66727 R
+ -
VCC V1
Large size of LCD panel
V2
LCD multiplexing driver
R V3 V3OUT V4OUT R V5OUT VEE Vci C1 VR
+ -
SEG1-SEG60
R
+ -
V3 COM1-COM16 V4
R
+ -
COMS1-COMS2
V5
0.47 F to 1 F + C2 V5OUT2 + 0.47 F to 1 F GND V5OUT3 + GND 0.47 F to 1 F Booster
Note : The capacitors for V1OUT and V4OUT must be inserted when 1/26 duty or 1/34 duty drives.
Figure 36 Operational Amplifier Output Stabilization Circuit Example when Driving Large Size of LCD Panel
63
HD66727
LCD driving current (IEE)*2 When I EE 15 A When 15 A IEE 40 A When I EE 40 A When 1/10, 1/18-duty drive (1 line, 2 lines) Capacitors for V1OUT to V5OUT must be inserted. When 1/26, 1/34-duty drive (3 lines, 4 lines) Capacitors for V1OUT to V5OUT must be inserted.
Capacitors for V1OUT and V4OUT Capacitors for V1OUT and V4OUT must be inserted. must be inserted. Capacitors for V1OUT and V4OUT And additional capacitors for other may be inserted after confirming the VnOUTs may be inserted after display quality. confirming the display quality.
Notes: 1. These relationships between LCD driving current (I EE ) and the external capacitors are applied to designing LCM, but they cannot guarantee the practical display quality. This display quality depends on LCD panel size and LCD material used, and it must be checked and confirmed with your LCD panel. 2. These LCD driving currents (I EE ) depend on the LCD driving voltage between VCC and VEE, and setting of VREF, VREFP and VREFP pins. 3. Especially the capacitors for V1OUT and V4OUT are most efficient for display quality. 4. This condition is an example when the frame frequency is 60Hz to 100Hz. If higher frame frequency is used, these external capacitors should be enhanced to prevent the cross-talk.
64
HD66727
When an Internal Booster and External Bleeder-Resistors are Used When the internal operational amplifiers cannot fully drive the LCD panel used, V1 to V5 voltages can be supplied through external bleeder-resistors (Figure 37). Here, the OPOFF pin must be set to the VCC level to turn off the internal operational amplifiers. Since the internal contrast adjuster is disabled in this case, contrast must be adjusted externally. Double- and triple-boosters can be used as they are.
OPOFF = VCC VCC
R R 2R V3OUT R R VR V4OUT V5OUT VEE Vci C1 VCC V1OUT V2OUT
HD66727
+ - + -
VCC V1 V2
+ - + - + -
V3 V4 V5
0.47 F to 1 F
+ C2 Booster
V5OUT2
+
GND
0.47 F to 1 F V5OUT3
+ to 1 F
GND
0.47 F
Notes: 1. Resistance of each external bleeder resistor should be 5 k to 15 k. 2. The bias current value for driving liquid-crystals can be varied by adjusting the resistance (2R) between the V2OUT and V3OUT pins. 3. The internal contrast-adjuster is disabled; contrast must be adjusted either by controlling the external variable resistor between VEE and V5OUT or Vci for the booster. 4. Vci is both a reference voltage and power supply for the booster; connect it to VCC directly or combine it with a transistor so that sufficient current can be obtained. 5. Vci must be smaller than VCC.
Figure 37 Power Supply Circuit Example Using External Bleeder-Resistor for LCD Drive Voltage Generation
65
HD66727
Contrast Adjuster
Multiplexing Drive System Contrast for an LCD controlled by the multiplexing drive method can be adjusted by varying the liquidcrystal drive voltage (potential difference between V CC and V5) through the CT bits of the contrast control instruction (electron volume function). See Figure 38 and Table 30. The value of a variable resistor (VR) can be adjusted within the range from 0.4 x R through 6.4 x R, where R is a reference resistance obtained by dividing the total resistance between VCC and V5. The HD66727 incorporates a voltage-follower operational amplifier for each of V1 to V5 to reduce current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal drive voltages. Thus, potential differences between VCC and V1 and between V EE and V5 must be 0.4V or greater. Note that the OPOFF pin must be grounded when using the operational amplifiers. 1/6 bias (V2 and V3 pins left open):
LCD drive voltage VLCD: 6R x (VCC - VEE)/(6R + VR) (VR = a value within the range from 0.4R to 6.4R) VLCD adjustable range: 0.484 x (VCC - VEE) VLCD 0.938 x (VCC - VEE) Potential difference between VCC and V1: R x (VCC - VEE)/(6R + VR) 0.4 (V) Potential difference between V5 and VEE: VR x (VCC - VEE)/(6R + VR) 0.4 (V)
1/4 bias (V2 and V3 pins short-circuited):
LCD drive voltage VLCD: 4R x (VCC - VEE)/(4R + VR) (VR = a value within the range from 0.4R to 6.4R) VLCD adjustable range: 0.385 x (VCC - VEE) VLCD 0.909 x (VCC - VEE) Potential difference between VCC and V1: R x (VCC - VEE)/(4R + VR) 0.4 (V) Potential difference between V5 and VEE: VR x (VCC - VEE)/(4R + VR) 0.4 (V)
66
HD66727
HD66727 R V2 R R V3 R R R VR CT
+ - + - + - + - + -
VCC
VCC V1 V2
V3 V4 V5
VEE
Figure 38 Contrast Adjuster
Table 30
CT3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Contrast-Adjust Bits (CT) and Variable Resistor Values
CT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Variable Resistor Value (VR) 6.4 R 6.0 R 5.6 R 5.2 R 4.8 R 4.4 R 4.0 R 3.6 R 3.2 R 2.8 R 2.4 R 2.0 R 1.6 R 1.2 R 0.8 R 0.4 R
Static Drive System Contrast for a statically-driven LCD, that is, annunciator display, can be adjusted through the AGND pin. The annunciators are driven statically by the potential difference between V CC and AGND. The AGND pin level must be equal to or greater than the GND level.
67
HD66727
LCD Panel Interface
The HD66727 can change the shift direction of common drivers COM1-COM32 and COMS1 and COMS2 and segment drivers SEG1-SEG60 with the CMS and SGS bits. These bits can be selected according to the mounting method such as the chip arrangement or wire leading. However, the output position of annunciator drivers ASEG1-ASEG12 cannot be changed, so adjust it by software.
HITACHI LTD. new HD66727 LCD CONTROLL with KeyScan
SEG60/1
HITACHI LTD. new HD66727 LCD CONTROLL with KeyScan
SEG1/60
COM1/32
COM17/16
Front of chip
COM16/17
Back of chip
COM32/1
COM32/1
COM16/17
a) Front of chip (CMS = "1" SGS = "1")
b) Back of chip(CMS = "1" SGS = "0")
SEG1/60
Front of chip
COM17/16
SEG60/1
COM16/17
COM32/1
COM32/1
COM16/17
Back of chip
COM1/32
HITACHI LTD. new HD66727 LCD CONTROLL with KeyScan
a) Front of chip(CMS = "0" SGS = "0")
HITACHI LTD. new HD66727 LCD CONTROLL with KeyScan
b) Back of chip(CMS = "0" SGS = "1")
Figure 39 LCD Module Interface Examples
68
HD66727
Segment Display and Annunciator Display
The HD66727 provides both segment display, which is driven by the multiplexing method, and annunciator display, which is driven statically. Annunciator display is driven at a logic operating voltage (V CC - AGND) and is thus also available while the LCD drive power supply is turned off. Accordingly, annunciator display is suitable for displaying marks during system standby, when it is desirable to reduce current consumption. It is available in the sleep mode, where internal multiplexing operations for character or segment display are halted. If an alternating signal is supplied to the EXM pin, it is also available in the standby mode, where the internal R-C oscillator is halted. Here, AGND must be equal to or above the GND level. Note that annunciator display cannot share character display drivers SEG and COM but require special drivers ASEG and ACOM that require long routing. Tables 31 to 34 compare segment display to annunciator display. Figure 40 shows annunciator drive output waveforms in two modes. Table 31
Item Number of driven elements
Comparison between Segment Display and Annunciator Display
Segment Display 40 each by 5-dot font width 48 each by 6-dot font width Annunciator Display 12
Blinking Segment drivers Common drivers LCD power supply Normal mode display
Impossible SEG1-SEG60 (shared with character display) COMS1, COMS2 VCC - V5 (LCD power supply necessary) Possible together with character display by multiplexing drive Impossible (SEG and COM output VCC) Impossible (SEG and COM output VCC)
Possible ASEG1-ASEG12 (independent of character display) ACOM VCC - AGND (LCD power supply unnecessary) Possible by static drive
Sleep mode display Standby mode display (without oscillation)
Possible by static drive Possible by supplying alternating signal to the EXM pin
69
HD66727
Table 32 Correspondence between Segment Display SEGRAM Addresses (ASEG) and Driver Signals when 5-Dot Font Width
Common Signal COMS1 COMS1 COMS1 COMS1 COMS2 COMS2 COMS2 COMS2 Segment Signal Bit 4 SEG1/21/41 SEG6/26/46 SEG11/31/51 SEG16/36/56 SEG1/21/41 SEG6/26/46 SEG11/31/51 SEG16/36/56 Bit 3 SEG2/22/42 SEG7/27/47 SEG12/32/52 SEG17/37/57 SEG2/22/42 SEG7/27/47 SEG12/32/52 SEG17/37/57 Bit 2 SEG3/23/43 SEG8/28/48 Bit 1 SEG4/24/44 SEG9/29/49 Bit 0 SEG5/25/45 SEG10/30/50 SEG15/35/55 SEG20/40/60 SEG5/25/45 SEG10/30/50 SEG15/35/55 SEG20/40/60
ASEG Address MSB 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 LSB 0 1 0 1 0 1 0 1
SEG13/33/53 SEG14/34/54 SEG18/38/58 SEG19/39/59 SEG3/23/43 SEG8/28/48 SEG4/24/44 SEG9/29/49
SEG13/33/53 SEG14/34/54 SEG18/38/58 SEG19/39/59
Table 33
Correspondence between Segment Display SEGRAM Addresses (ASEG) and Driver Signals when 6-Dot Font Width
Common Segment Signal Signal Bit 7 Bit 6 Bit 5 COMS1 COMS1 COMS1 COMS1 COMS2 COMS2 COMS2 COMS2 * * * * * * * * * * * * * * * *
ASEG Address MSB 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 LSB 0 1 0 1 0 1 0 1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SEG1/25/ SEG2/26/ SEG3/27/ SEG4/28/ SEG5/29/ SEG6/30/ 49 50 51 52 53 54 SEG7/31/ SEG8/32/ SEG9/33/ SEG10/ 55 56 57 34/58 SEG13/ 37 SEG19/ 43 SEG14/ 38 SEG20/ 44 SEG15/ 39 SEG21/ 45 SEG16/ 40 SEG22/ 46 SEG11/ 35/59 SEG17/ 41 SEG23/ 47 SEG12/ 36/60 SEG18/ 42 SEG24/ 48
SEG1/25/ SEG2/26/ SEG3/27/ SEG4/28/ SEG5/29/ SEG6/30/ 49 50 51 52 53 54 SEG7/31/ SEG8/32/ SEG9/33/ SEG10/ 55 56 57 34/58 SEG13/ 37 SEG19/ 43 SEG14/ 38 SEG20/ 44 SEG15/ 39 SEG21/ 45 SEG16/ 40 SEG22/ 46 SEG11/ 35/59 SEG17/ 41 SEG23/ 47 SEG12/ 36/60 SEG18/ 42 SEG24/ 48
70
HD66727
Table 34
AAN Address MSB 0 0 0 0 0 0 0 0 1 LSB 0 1 0 Common Signal ACOM ACOM ACOM
Correspondence between Annunciator Display Addresses (AAN) and Driver Signals
Segment Signal Bits 7, 6 ASEG1 ASEG5 ASEG9 Bits 5, 4 ASEG2 ASEG6 ASEG10 Bits 3, 2 ASEG3 ASEG7 ASEG11 Bits 1, 0 ASEG4 ASEG8 ASEG12
Note: The annunciator is turned on when the corresponding even bit (bit 6, 4, 2, or 0) is 1, and the turnedon annunciator blinks when the corresponding odd bit (bit 7, 5, 3, or 1) is 1.
i) Normal mode and sleep mode
VCC level ACOM VCC level ASEG1 VCC level ASEG2 1 frame AGND level VCC level AGND level
VCC level
VCC level Display off
AGND level
Display on
ii) Standby mode (without oscillation) 1 frame VCC level EXM (Input) VCC level ACOM VCC level ASEG1 AGND level VCC level ASEG2 AGND level AGND level Display on AGND level VCC level Display off AGND level VCC level VCC level
Note: If annunciator display is unnecessary during standby mode, make sure to fix the EXM pin to the VCC or GND level and set the annunciator display ON bit (DA) to 0. This will prevent dark display and liquid-cell deterioration due to DC bias application on liquid crystal cells.
Figure 40 Annunciator Drive Output Waveforms
71
HD66727
Vertical Smooth Scroll
The HD66727 can scroll in the vertical direction in units of raster-rows. This function is achieved by writing character codes into DDRAM area that is not being used for display. In other words, since DDRAM corresponds to a 5-line x 12-character display, one of the lines can be used to achieve continuous smooth vertical scroll even in a 4-line display. Here, after the fifth line is displayed, the first line is displayed again. Specifically, this function is controlled by incrementing or decrementing the value in the display-start line bits (SL2 to SL0) and display-start raster-row bits (SN2 to SN0) by 1. For example, to smoothly scroll up, first set SN2 to SN0 to 000, and increment SL2 to SL0 by 1 from 000 to 111 to scroll seven raster-rows. Then increment SN2 to SN0 to 001, and again increment SL2 to SL0 by 1 from 000 to 111. To start displaying and scrolling from the first raster-row of the second line, update the first line of DDRAM data as desired during its non-display period. Figure 41 shows an example of vertical smooth scrolling and Figure 42 shows an example of setting instructions for vertically scrolling upward in a 4-line display (NL1 and NL0 = 11).
72
HD66727
Set initial data to all DDRAM addresses
1) Not scrolled * SN2-0 = 000 * SL2-0 = 000 9) 8 raster-rows scrolled up * SN2-SN0 = 001 * SL2-SL0 = 000
Update the first line of DDRAM data
10) 9 raster-rows scrolled up * SL2-SL0 = 001
2) 1 raster-rows scrolled up * SL2-SL0 = 001
3) 2 raster-rows scrolled up * SL2-SL0 = 010
11) 10 raster-rows scrolled up * SL2-SL0 = 010
4) 3 raster-rows scrolled up * SL2-SL0 = 011
12) 11 raster-rows scrolled up * SL2-SL0 = 011
5) 4 raster-rows scrolled up * SL2-SL0 = 100
13) 12 raster-rows scrolled up * SL2-SL0 = 100
6) 5 raster-rows scrolled up * SL2-SL0 = 101
14) 13 raster-rows scrolled up * SL2-SL0 = 101
7) 6 raster-rows scrolled up * SL2-SL0 = 110
15) 14 raster-rows scrolled up * SL2-SL0 = 110
8) 7 raster-rows scrolled up * SL2-SL0 = 111
16) 15 raster-rows scrolled up * SL2-SL0 = 111
Figure 41 Example of Vertical Smooth Scrolling
73
HD66727
Scroll up display
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0
0 0
0 0
0 1
1 1
0 0 0 0
CT 0 0
SN2= 0 SN1/0 = 00 and SL2-SL0 = 000 (1st raster-row of 1st line displayed at the top)
Set initial character codes of 5 lines to all DDRAM addresses
0
0
0
1
1
0
0
0
0
1
CPU Wait 0 0 0 1 1 0 0 0 1 0
Scroll up 1 raster-row (2nd raster-row of 1st line displayed at the top) Scroll up 2 raster-rows (3rd raster-row of 1st line displayed at the top) Scroll up 3 raster-rows (4th raster-row of 1st line displayed at the top) Scroll up 4 raster-rows (5th raster-row of 1st line displayed at the top))
CPU Wait 0 0 0 1 1 0 0 0 1 1
CPU Wait 0 0 0 1 1 0 0 1 0 0
CPU Wait
0
0
0
1
1
0
0
1
1
1
CPU Wait 0 0 0 1 1 0 1 0 0 0
Scroll up 7 raster-rows (8th raster-row of 1st line displayed at the top) Scroll up 8 raster-rows (1st raster-row of 2nd line displayed at the top) (While 1st line is not being displayed but 2nd to 5th lines are being displayed)
CPU Wait
Update 1st-line (address 00H to 1BH) character codes in DDRAM 0 0 0 1 1 0 1 0 0 1
CPU Wait
Scroll up 9 raster-rows (2nd raster-row of 2nd line displayed at the top)
0
0
0
1
1
0
1
1
1
1
CPU Wait 0 0 0 1 1 1 0 0 0 0
Scroll up 15 raster-rows (8th raster-row of 2nd line displayed at the top) Scroll up 16 raster-rows (1st raster-row of 3rd line displayed at the top) (While 2nd line is not being displayed but 1st and 3rd to 5th lines are being displayed)
CPU Wait
Update 2nd-line (address 10H to 1BH) character codes in DDRAM 0 0 0 1 1 1 0
0
0
1
CPU Wait
Scroll up 17 raster-rows (2nd raster-row of 3rd line displayed at the top)
Figure 42 Example of Setting Instructions for Vertical Smooth Scroll (4-line display (NL1 and NL0 = 11))
74
HD66727
Line-Cursor Display
The HD66727 can assign a cursor attribute to an entire line corresponding to the address counter value by setting the LC bit to 1 (Table 35). One of three line-cursor modes can be selected: a black-white inverting blink cursor (B/W = 1), an underline cursor (C = 1), and a blink cursor (B = 1). The blink cycle for a blackwhite inverting cursor and for a blink cursor is 32 frames. These line-cursors are suitable for highlighting an index and/or marker, and for indicating an item in a menu with a cursor or an underline. Figures 43 to 45 show three line-cursor examples. Table 35 Address Counter Value and Line-Cursor
Selected Line for Line-Cursor Entire 1st line (12 characters) Entire 2nd line (12 characters) Entire 3rd line (12 characters) Entire 4th line (12 characters) Entire 5th line (12 characters)
Address Counter Value (AC) "00"H to "0B"H "10"H to "1B"H "20"H to "2B"H "30"H to "3B"H "40"H to "4B"H
75
HD66727
Alternates every 32 frames
Figure 43 Example of Black-White Inverting Blink Cursor (LC = 1; B/W = 1)
76
HD66727
Figure 44 Example of Underline Cursor (LC = 1; C = 1)
77
HD66727
Alternates every 32 frames
Figure 45 Example of Blink Cursor (LC = 1; B = 1)
78
HD66727
Double-Height Display
The HD66727 can double the height of any desired line from the first to third lines. A line can be selected by the DL3 to DL1 bits as listed in Table 36. All the standard font characters stored in the CGROM and CGRAM can be doubled in height, providing an easy-to-see display. Note that there should be no space between lines for double-height display (Figure 46). Table 36
DL3 0 0 0 0 1 1 1 1 DL2 0 0 1 1 0 0 1 1
Double-Height Display Specifications
DL1 0 1 0 1 0 1 0 1 2-Line Display (NL1, NL0 = 01) 1st & 2nd lines: normal 1st line: double-height Disabled 1st line: double-height 1st & 2nd lines: normal 1st line: double-height Disabled 1st line: double-height 3-Line Display (NL1, NL0 = 10) 1st to 3rd lines: normal 1st line: double-height 2nd line: normal 2nd line: double-height 1st line: normal Disabled Disabled 1st line: double-height 2nd line: normal 2nd line: double-height 1st line: normal Disabled 4-Line Display (NL1, NL0 = 11) 1st to 4th lines: normal 1st line: double-height 2nd & 3rd lines: normal 2nd line: double-height 1st & 3rd lines: normal 1st & 2nd lines: double-height 3rd line: double-height 1st & 2nd lines: normal Disabled Disabled 1st & 2nd lines: double-height
79
HD66727
i) 3-line display example (DL1 = 0, DL2 = 1)
1st line: normal display
2nd line: double-height display
ii) 4-line display example (DL = 1, DL2 = 0, DL3 = 0)
1st line: double-height display
2nd line: normal display
3rd line: normal display
Figure 46 Double-Height Display Examples
80
HD66727
Double-Width Display
When the font width bit (FW) is set, the width is 5 dots or 6 dots. When FW = 0, the font width is 5 dots and can be displayed horizontally up to 12 digits. However, the spaces between characters should hold the ITO wiring on the LCD glass. When FW = 1, the font width is 6 dots and can be displayed horizontally up to 10 digits. However, when displaying double-width characters with the font in the CGROM, a special double-width font is needed. In that case, a custom ROM is used. Double-height characters can be displayed by setting the register in combination with the above doublewidth display.
Note: This display can be performed with the custom CGROM.
Figure 47 Triple-Width Display Examples
81
HD66727
LED/Back Light Control
The HD66727 has three LED ports to control the LED and back light, which need current driving, and three general ports, which do not need current driving. However, the sink current in the LED port output is up to 3 mA. If the back light or LED needs more current, increase the current width with the transistor. Table 37 LED Driving and General Output Port
LED Driving/General Output Port LSB 0 1 1 Bit 7 * Bit 6 * Bit 5 PORT2 Bit 4 PORT1 Bit 3 PORT0 Bit 2 LED2 Bit 1 LED1 Bit 0 LED0
AAN Address MSB 0
VCC
HD66727
LED0 LED1 LED2
LED display
Back light
PORT0 PORT1 PORT2
GND
Figure 48 LED Driving Control Circuit Examples
82
HD66727
Partial-Display-Off Function
The HD66727 can program the number of display lines (NL bits), divide the internal operating frequency by four (OSC bit), and adjust the display contrast (CT bits). Combining these functions, the HD66727 can turn off the second and/or subsequent lines, displaying only the characters in the first line to reduce internal current consumption (partial-display-off function). This function is suitable for calendar or time display, which needs to be continuous during system standby with minimal current consumption. Here, the second to fourth non-displayed lines are constantly driven by the deselection level voltage, thus turning off the LCD for the lines. Note that internal clock frequency is reduced to a quarter, quadrupling execution time of each instruction; MPU data transfer rate must be appropriately adjusted. Moreover, as being affected by the NL1 bit and the OSC1 bit, the key-scan cycle for partial-display-off is not the same as that for normal display. Adjust the key-scan cycle by the KF1 and KF0 bits. Table 38 lists partial-display-off function specifications and Figure 49 shows a sample display using the partial-display-off function Table 38 Partial-Display-Off Function
Normal 4-Line Display 1st to 4th lines displayed Possible Possible 160 kHz 160 kHz (OSC = 0) 2.7 kHz (1/34 duty ratio) 78 Hz 320 to 2,560 clock cycles (Clock cycle = 1 / internal operating frequency) Partially-Off Display Only 1st line displayed Possible Possible 160 kHz 40 kHz (OSC = 1) 0.7 kHz (1/10 duty ratio) 66 Hz 160 to 1,280 clock cycles (Clock cycle = 1 / internal operating frequency)
Function Item Character display Segment display Annunciator display R-C oscillation frequency Internal operating frequency LCD single-line drive frequency Frame frequency Key scan cycle
Note: Select an optimum LCD drive voltage (between V CC and V5) for the multiplexing duty ratio used, using a reference voltage input pin (Vci) for the booster or the contrast adjust bits (CT) .
83
HD66727
Display available (driven with selection level) Display available (driven with selection level)
Display unavailable (driven with deselection level)
Figure 49 Example of Partially-Off Display (date and time indicated)
84
HD66727
Sleep Mode
Setting the sleep mode bit (SLP) to 1 puts the HD66727 in the sleep mode, where the device halts all the internal display operations except for annunciator display and key scan operations, thus reducing current consumption. Specifically, character and segment displays, which are controlled by the multiplexing drive method, are completely halted. Here, all the SEG (SEG1 to SEG60) and COM (COM1 to COM34) pins output the VCC level, resulting in no display. If the AMP bit is set to 0 in the sleep mode, the LCD drive power supply can be turned off, reducing the total current consumption of the LCD module. Annunciators can be normally displayed in the sleep mode. Since they are driven at logic operating power supply voltage (VCC - AGND), they are available even if the LCD power supply is turned off (AMP = 0). This function allows time and alarm marker indication during system standby with reduced current consumption. During the sleep mode, no instructions can be accepted for character/segment display and neither DDRAM, CGRAM, nor SEGRAM can be accessed. The key scan circuit operates normally in the sleep mode, thus allowing normal key scan and key scan interrupt generation. All keys can be scanned while only displaying annunciators. For details, refer to the Key Scan Control section. Table 38 compares the functions of the sleep mode and standby mode. Table 38
Function Character display Segment display Annunciator display R-C oscillation Key scan
Comparison of Sleep Mode and Standby Mode
Sleep Mode (SLP = 1) Turned off Turned off Can be turned on Operates normally Can operate normally Standby Mode (STB = 1) Turned off Turned off Can be turned on when an alternating signal is supplied to the EXM pin Halted Halted but IRQ* can be generated
85
HD66727
Standby Mode
Setting the standby mode bit (STB) to 1 puts the HD66727 in the standby mode, where the device stops completely, halting all internal operations including the R-C oscillator, thus further reducing current consumption compared to that in the sleep mode. Specifically, character and segment displays, which are controlled by the multiplexing drive method, are completely halted. Here, all the SEG (SEG1 to SEG60) and COM (COM1 to COM34) pins output the V CC level, resulting in no display. If the AMP bit is set to 0 in the standby mode, the LCD drive power supply can be turned off. Annunciators can be displayed simply by supplying an approximately 40-Hz alternating signal for the LCD drive signals to the EXM pin externally. If annunciator display is unnecessary during the standby mode, the EXM pin must be fixed to the VCC or GND level and the annunciator display on bit (DA) set to 0. During the standby mode, no instructions can be accepted other than those for annunciator display, the start-oscillator instruction, and the key scan interrupt generation enable instruction. To cancel the standby mode, issue the start oscillator instruction to stabilize R-C oscillation before setting the STB bit to 0. Although key scan is halted in the standby mode, the HD66727 can detect four key inputs connected with strobe signal KST0, thus generating the key scan interrupt (IRQ*). This means, the system can be activated from the completely inactive state. For details, refer to the Key Scan Control section. Figure 50 shows the procedure for setting and canceling the standby mode.
Turn off the LCD power supply: AMP = 0 Set standby mode: STB = 1 Supply an external alternating signal to the EXM pin Only for annunciator display; set the DA bit to 0 when annunciator display is not necessary.
Standby mode (only annunciator display is available)
Issue the start-oscillator instruction Wait at least 10 ms Cancel standby mode: STB = 0 Turn on the LCD drive power supply: AMP = 1
Figure 50 Procedure for Setting and Canceling Standby Mode
86
HD66727
Absolute Maximum Ratings *
Item Power supply voltage (1) Power supply voltage (2) Input voltage Operating temperature Storage temperature Note: * Symbol VCC VCC - VEE Vt Topr Tstg Unit V V V C C Value -0.3 to +7.0 -0.3 to +15.0 -0.3 to VCC + 0.3 -30 to +75 -55 to +110 4 Notes** 1 1, 2 1
If the LSI is used above these absolute maximum ratings, it may become permanently damaged. Using the LSI within the following electrical characteristic limits is strongly recommended for normal operation. If these electrical characteristic conditions are also exceeded, the LSI will malfunction and cause poor reliability.
87
HD66727
DC Characteristics (VCC = 2.4 to 5.5V, Ta = -30 to +75C*3)
Item Input high voltage Input low voltage Input low voltage Output high voltage (1) (SDA pin) Output low voltage (1) (SDA pin) Output low voltage (1) (SDA pin) Output high voltage (2) (KST0-7, IRQ* pins) Output low voltage (2) (KST0-7, IRQ* pins) Output high voltage (3) (LED0-2 pins) Output low voltage (3) (LED0-2 pins) Output high voltage (4) (PORT0-2 pins) Output low voltage (4) (PORT0-2 pins) Driver ON resistance (COM pins) Driver ON resistance (SEG pins) I/O leakage current Pull-up MOS current 1 (KIN0-3 pins) Pull-up MOS current 2 (RESET* pins) Symbol Min VIH VIL VIL VOH1 VOL1 V OL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 RCOM RSEG I Li -Ip1 -Ip2 0.7V CC -0.3 -0.3 0.75V CC -- -- 0.7V CC -- 0.75V CC -- 0.75V CC -- -- -- -1 1 5 -- Typ -- -- -- -- -- -- -- -- -- 0.2 -- -- 2 2 -- 10 50 30 Max VCC Unit Test Condition V VCC = 2.4 to 3.0V VCC = 3.0 to 5.5V I OH = -0.1 mA VCC = 2.4 to 4.5V, IOL = 0.4 mA VCC = 4.5 to 5.5V, IOL = 1.0 mA -I OH = 0.5 A, VCC = 3V I OL = 0.1 mA -I OH = 0.1 mA I OL = 3 mA VCC = 3V -I OH = 0.1 mA I OL = 0.1 mA Id = 0.05 mA, VLCD = 4V Id = 0.05 mA, VLCD = 4V Vin = 0 to VCC VCC = 3V, Vin = 0V VCC = 3V, Vin = 0V R-C oscillation, VCC = 3V, fOSC = 160 kHz (1/34 duty) R-C oscillation, VCC = 3V, fOSC = 160 kHz (1/34 duty) No Rf oscillation, VCC = 3V, Ta = 25C 10, 11 Notes 6 6 6 7 5 5 5 5 5 5 5 5 8 8 9
0.15V CC V 0.6 -- V V
0.2V CC V 0.4 -- V V
0.2V CC V -- 1.0 -- V V V
0.2V CC V 20 30 1 40 120 60 k k A A A A
Current consumption I OP during normal operation (VCC-GND) Current consumption during sleep mode (VCC-GND) Current consumption during standby mode (VCC-GND) I SL
--
25
--
A
10, 11
I ST
--
0.1
5
A
10, 11
Note: For the numbered notes, refer to the Electrical Characteristics Notes section following these tables.
88
HD66727
DC Characteristics (VCC = 2.4 to 5.5V, Ta = -30 to +75C*3) (cont)
Item Symbol Min -- 3.0 3.0 Typ 25 -- -- Max 60 13.0 13.0 Unit Test Condition A V V VCC - VEE = 7V, f OSC = 160 kHz V2-V3 short-circuited V2-V3 open Notes 11 12 12 LCD drive power supply I EE current (VCC-VEE) LCD drive voltage with 1/4 bias (VCC-VEE) LCD drive voltage with 1/6 bias (VCC-VEE) VLCD1 VLCD2
Note: For the numbered notes, refer to the Electrical Characteristics Notes section following these tables.
Booster Characteristics
Item Output voltage (V5OUT2 pin) Output voltage (V5OUT3 pin) Input voltage Symbol VUP2 Min 8.0 Typ 8.8 Max -- Unit V Test Condition VCC = Vci = 4.5V, I O = 0.1 mA, C = 1 F, f OSC = 160 kHz, Ta = 25C VCC = Vci = 2.7V, I O = 0.1 mA, C = 1 F, f OSC = 160 kHz, Ta = 25C Vci VCC Notes 15
VUP3
7.0
7.9
--
V
15
VCi
1.0
--
5.0
V
15
Note: For the numbered notes, refer to the Electrical Characteristics Notes section following these tables.
AC Characteristics (VCC = 2.4 to 5.5V, Ta = -30 to +75C*3)
Clock Characteristics
Item External clock frequency External clock duty ratio External clock rise time External clock fall time Internal Rf oscillation frequency Symbol f cp Duty t rcp t fcp t OSC Min 20 45 -- -- 120 Typ 160 50 -- -- 160 Max 350 55 0.2 0.2 200 Unit kHz % s s kHz Rf = 150 k, VCC = 3V Test Condition Notes 13 13 13 13 14
Note: For the numbered notes, refer to the Electrical Characteristics Notes section following these tables.
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HD66727
Clock-Synchronized Serial Interface Timing
Item Serial clock cycle time Serial clock high-level width Serial clock low-level width Serial clock rise/fall time Chip select set-up time Chip select hold time Serial input data set-up time Serial input data hold time Serial output data delay time Serial output data hold time Symbol t SCYC t SCH t SCL t scr , t scf t CSU t CH t SISU t SIH t SOD t SOH Min 1 400 400 -- 60 200 200 200 -- 0 Typ -- -- -- -- -- -- -- -- -- -- Max 20 -- -- 50 -- -- -- -- 400 -- Unit s ns ns ns ns ns ns ns ns ns Test Condition Figures 57 and 58 Figures 57 and 58 Figures 57 and 58 Figures 57 and 58 Figures 57 and 58 Figures 57 and 58 Figure 57 Figure 57 Figure 58 Figure 59
I2C bus Interface Timing
Item SCL clock cycle time SCL clock high-level width SCL clock low-level width SCL/SDA rise/fall time Bus free time Bus free time Start hold time Retransmit start set-up time Stop set-up time SDA data set-up time SDA data set-up time SDA data hold time Symbol t SCL t SCLH t SCLL t sr, t sf t BUF t BUF t STAH t STAS t STOS t SDAS t SDAS t SDAH Min 2 500 1000 -- 140 100 500 500 500 140 100 0 Typ -- -- -- -- -- -- -- -- -- -- -- -- Max 20 -- -- 300 -- -- -- -- -- -- -- -- Unit s ns ns ns ns ns ns ns ns ns ns ns Test Condition Figure 59 Figure 59 Figure 59 Figure 59 VCC = 2.4-4.5V VCC = 4.5-5.5V Figure 59 Figure 59 Figure 59 VCC=2.4V-4.5V VCC =4.5V-5.5V Figure 59
Reset Timing
Item Reset low-level width Symbol t RES Min 10 Typ -- Max -- Unit ms Test Condition Figure 60
90
HD66727
Electrical Characteristics Notes
1. All voltage values are referred to GND = 0V. If the LSI is used above the absolute maximum ratings, it may become permanently damaged. Using the LSI within the given electrical characteristic is strongly recommended to ensure normal operation. If these electrical characteristic are exceeded, the LSI may malfunction or exhibit poor reliability. 2. VCC > V1 V2 V3 V4 V5 > VEE must be maintained. 3. For bare die products, specified at 75C. 4. For bare die products, specified by the common die shipment specification. 5. The following four circuits are I/O pin configurations except for liquid crystal display output (Figure 51).
Pins: SCL, ID1/CS*, ID0, OSC1, OPOFF, IM, EXM, TEST VCC PMOS NMOS (Pull-up MOS) Pins: KIN3 to KIN0, RESET* Pins: KST7 to KST0, IRQ* LED2 to LED0, PORT2 to PORT0
VCC PMOS
VCC PMOS
VCC PMOS NMOS
NMOS
GND VCC Pin: SDA (Pull-up MOS) PMOS VCC
GND
GND
PMOS (Input circuit) NMOS VCC PMOS (Tri-state output circuit) Output enable Output data
NMOS
GND IM
Figure 51 I/O Pin Configurations 6. The TEST pin must be grounded and the ID1 and ID0, IM, EXM, and OPOFF pins must be grounded or connected to V CC. 7. Corresponds to the high output for clock-synchronized serial interface.
91
HD66727
8. Applies to resistor values (RCOM ) between power supply pins V CC, V1OUT, V4OUT, V5OUT and common signal pins (COM1 to COM32, COMS1, and COMS2), and resistor values (R SEG) between power supply pins VCC, V2OUT, V3OUT, V5OUT and segment signal pins (SEG1 to SEG60). 9. This excludes the current flowing through pull-up MOSs and output drive MOSs. 10. This excludes the current flowing through the input/output units. The input level must be fixed high or low because through current increases if the CMOS input is left floating. 11. The following shows the relationship between the operation frequency (fOSC) and current consumption (I CC) (Figure 52).
VCC = 3V 1/34 duty 1/26 duty 1/18 duty 1/10 duty VCC = 3V Display on (typ.) 80 60 40 VREF-VREFM short-circuited 20 Standby mode (typ.) 0 0 50 100 150 200 250 0 3 4 5 6 7 8 9 10 11 VREF-VREFP short-circuited VREF left disconnected VREF = VREFP = VREFM short-circuited
40 30 Icc (A)
Sleep mode (typ.)
20
10
IEE (A)
R-C oscillation frequencies: fosc (kHz)
LCD drive voltages: VLCD (V)
Figure 52 Relationship between the Operation Frequency and Current Consumption 12. Each COM and SEG output voltage is within 0.15V of the LCD voltage (V CC, V1, V2, V3, V4, V5) when there is no load. 13. Applies to the external clock input (Figure 53).
Th Oscillator Open OSC1 OSC2 0.7VCC 0.5VCC 0.3VCC trcp t fcp Tl Th Th+Tl
Duty =
X 100%
Figure 53 External Clock Supply
92
HD66727
14. Applies to the internal oscillator operations using oscillation resistor Rf (Figure 54).
OSC1 Rf OSC2 Referential data 200
Since the oscillation frequency varies depending on the OSC1 and OSC2 pin capacitance, the wiring length to these pins should be minimized.
160 150
fOSC (kHz)
100 VCC = 3 V (typ.) 50
VCC = 5 V (typ.)
0 100 160 200
300
400
500 Rf (k)
600
700
800
Figure 54 Internal Oscillation 15. Booster characteristics test circuits are shown in Figure 55.
( Triple boosting )
( Double boosting )
VCC Vci C1 C2 V5OUT2 + V5OUT3 VEE GND + 1 F 1 F
VCC
Vci C1 C2 1 F + 1 F 1 F
V5OUT2 + V5OUT3 + GND VEE
Figure 55 Booster
93
HD66727
Referential data VUP2 = VCC - V5OUT2; VUP3 = VCC - V5OUT3 (i) Relation between the obtained voltage and input voltage Double boosting 11 10 9 8 VUP2 (V) 7 6 5 4 2.0 3.0 4.0 Vci (V) Vci = VCC, fcp =160 kHz, Ta = 25C (ii) Relation between the obtained voltage and temperature Double boosting 9.5 9.0 VUP2 (V) 8.5 8.0 7.5 -60 typ. 8.5 Triple boosting 5.0 15 typ. 14 13 12 11 VUP3 (V) 10 9 8 7 6 Triple boosting typ.
2.0
3.0
4.0 Vci (V)
5.0
Vci = VCC, fcp =160 kHz, Ta = 25C
8.0 VUP3 (V) 7.5 7.0 6.5 -60
typ.
-20 0 20 Ta (C)
60
100
-20 0 20 Ta (C)
60
100
Vci = VCC = 4.5 V, Rf = 180 k, Io = 0.1 mA (iii) Relation between the obtained voltage and capacitance Double boosting 9.0 8.5 VUP2 (V) 8.0 7.5 7.0 typ.
Vci = VCC = 2.7 V, Rf = 150 k, Io = 0.1 mA
Triple boosting 8.0 7.5 VUP3 (V) 7.0 6.5 typ. min.
0.5
1.0 C (F)
1.5
6.0
0.5
1.0 C (F)
1.5
Vci = VCC = 4.5 V, Rf = 180 k, Io = 0.1 mA
Vci = VCC = 2.7 V, Rf = 150 k, Io = 0.1 mA
Figure 55 Booster (cont)
94
HD66727
Double boosting 9.0 8.5 8.0 VUP2 (V) VUP3 (V) 7.5 7.0 6.5 6.0 0.0 0.5 1.0 IO (mA) Vci = VCC = 4.5 V, Rf = 180 k, Ta = 25C 1.5 2.0 typ. 8.0 7.0 6.0 5.0 4.0 3.0 2.0 0.0 0.5 1.0 IO (mA) Vci = VCC = 2.7 V, Rf = 150 k, Ta = 25C 1.5 2.0 typ. Triple boosting
Load Circuits
AC Characteristics Test Load Circuits
Data bus : SDA Test Point
50 pF
Figure 56 Load Circuit
95
HD66727
Timing Characteristics
Clock-Synchronized Serial Interface Timing
Start : S
End : P
CS*
VIL t SCYC t CSU VIH tscr t SCH VIH VIH VIL t SISU VIH VIL t SIH VIH Valid data VIL Valid data VIL tscf t CWL t CH VIH
VIL
SCL
SDA VIL
Figure 57 Clock-Synchronized Serial Interface Input Timing
Start : S
End : P
CS* VIL tSCYC tCSU tscr tSCH tscf tCWL
VIH VIL
tCH
VIH SCL VIL tSOD VIL
VIH VIH VIL VIL
VIH
tSOH
VOH1 SDA VOH1 Output data Output data
VOH1 VOL1
Figure 58 Clock-Synchronized Serial Interface Output Timing
96
HD66727
I2C Bus Interface Timing
Start :S Restart : Sr Stop : P
Stop : P
SDA
VIH
VIH VIL t BUP t STAH VIH
VIH VIL t SDAH t SCL t SCLH VIH VIL t sr t STAS
VIH
VIH VIL t SDAS t STOPS VIL
VIH VIL
VIH
SCL t sf
VIL t SCLL
Figure 59 I2C Bus Interface Timing Reset Timing
t RES
RESET*
VIL
VIL
Figure 60 Reset Timing
97

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